產品詳情

Number of channels 8 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 90 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (μA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 90 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (μA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 20 228.702 mm2 24.33 x 9.4 SOIC (DW) 20 131.84 mm2 12.8 x 10.3 TSSOP (PW) 20 41.6 mm2 6.5 x 6.4
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 11 ns at 5 V
  • Inputs Are TTL-Voltage Compatible
  • 3-State Inverting Outputs Drive Bus Lines Directly
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 11 ns at 5 V
  • Inputs Are TTL-Voltage Compatible
  • 3-State Inverting Outputs Drive Bus Lines Directly

The ’ACT533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverted levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

(OE)\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The ’ACT533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverted levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

(OE)\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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類型 標題 下載最新的英語版本 日期
* 數據表 SN54ACT533, SN74ACT533 數據表 (Rev. C) 2002年 10月 8日

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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