產品詳情

Bits (#) 7 Data rate (max) (Mbps) 12 Topology Push-Pull Vin (min) (V) 4.7 Vin (max) (V) 5.5 Applications IEEE1284 Features Output enable, Partial power down (Ioff), Single supply Technology family ACT Supply current (max) (mA) 1.5 Rating Catalog Operating temperature range (°C) 0 to 70
Bits (#) 7 Data rate (max) (Mbps) 12 Topology Push-Pull Vin (min) (V) 4.7 Vin (max) (V) 5.5 Applications IEEE1284 Features Output enable, Partial power down (Ioff), Single supply Technology family ACT Supply current (max) (mA) 1.5 Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 20 131.84 mm2 12.8 x 10.3 SOP (NS) 20 98.28 mm2 12.6 x 7.8 SSOP (DB) 20 56.16 mm2 7.2 x 7.8 TSSOP (PW) 20 41.6 mm2 6.5 x 6.4
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 20 ns at 5 V
  • 3-State Outputs Directly Drive Bus Lines
  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 20 ns at 5 V
  • 3-State Outputs Directly Drive Bus Lines
  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications

The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.

The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.

The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.

The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.

The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.

The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.
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類型 標題 下載最新的英語版本 日期
* 數據表 SN54ACT1284, SN74ACT1284 數據表 (Rev. D) 2003年 10月 23日

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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