產品詳情

Technology family ACT Bits (#) 16 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ACT Bits (#) 16 Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 20 131.84 mm2 12.8 x 10.3 SOP (NS) 20 98.28 mm2 12.6 x 7.8
  • Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Reduces Undershoot and Overshoot Caused By Line Reflections
  • Repetitive Peak Forward Current ...IFRM = 100 mA
  • Inputs Are TTL-Voltage Compatible
  • Low Power Consumption (Like CMOS)
  • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Reduces Undershoot and Overshoot Caused By Line Reflections
  • Repetitive Peak Forward Current ...IFRM = 100 mA
  • Inputs Are TTL-Voltage Compatible
  • Low Power Consumption (Like CMOS)
  • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or pulldown resistors.

The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state.

This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or pulldown resistors.

The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state.
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類型 標題 下載最新的英語版本 日期
* 數據表 SN74ACT1073 數據表 (Rev. A) 2002年 11月 1日

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓