LM3881
- Easiest Method to Sequence Rails
- Power-Up and Power-Down Control
- Tiny Footprint
- Low Quiescent Current of 80 μA
- Input Voltage Range of 2.7 V to 5.5 V
- Output Invert Feature
- Timing Controlled by Small Value External
Capacitor
The LM3881 Simple Power Sequencer offers the easiest method to control power up and power down of multiple power supplies (switching or linear regulators). By staggering the start-up sequence, it is possible to avoid latch conditions or large inrush currents that can affect the reliability of the system.
Available in VSSOP-8 package, the Simple Sequencer contains a precision enable pin and three open-drain output flags. When the LM3881 is enabled, the three output flags will sequentially release, after individual time delays, thus permitting the connected power supplies to start up. The output flags will follow a reverse sequence during power down to avoid latch conditions. Time delays are defined using an external capacitor and the output flag states can be inverted by the user.
技術(shù)文檔
| 頂層文檔 | 類型 | 標(biāo)題 | 格式選項 | 下載最新的英語版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | LM3881 Simple Power Sequencer With Adjustable Timing 數(shù)據(jù)表 (Rev. D) | PDF | HTML | 2014年 12月 10日 | ||
| 選擇指南 | 電源管理指南 2018 (Rev. K) | 2018年 7月 31日 | ||||
| 選擇指南 | 電源管理指南 2018 (Rev. R) | 2018年 6月 25日 | ||||
| 技術(shù)文章 | How to manage processor power during uncontrolled power off | PDF | HTML | 2018年 6月 21日 | |||
| 技術(shù)文章 | Sequencing solutions: simple, reliable and cost-effective | PDF | HTML | 2017年 9月 27日 | |||
| 技術(shù)文章 | A simple six-channel power-rail sequencing solution | PDF | HTML | 2015年 11月 16日 | |||
| 應(yīng)用手冊 | Power Supply Design Considerations for Modern FPGAs | 2010年 2月 2日 |
設(shè)計與開發(fā)
如需其他信息或資源,請點(diǎn)擊以下任一標(biāo)題進(jìn)入詳情頁面查看(如有)。
LM3881EVAL — 用于 LM3881 電源序列發(fā)生器的評估板
This evaluation board is designed to permit the designer to connect it directly to the Enable or Remote ON/Off pins of power supply devices of an existing system to facilitate system sequencing. Upon enabling the device, the three open drain output flags will rise in sequential order, 1-2-3. Once (...)
PSPICE-FOR-TI — PSpice? for TI 設(shè)計和仿真工具
借助?PSpice for TI 的設(shè)計和仿真環(huán)境及其內(nèi)置的模型庫,您可對復(fù)雜的混合信號設(shè)計進(jìn)行仿真。創(chuàng)建完整的終端設(shè)備設(shè)計和原型解決方案,然后再進(jìn)行布局和制造,可縮短產(chǎn)品上市時間并降低開發(fā)成本。?
在?PSpice for TI 設(shè)計和仿真工具中,您可以搜索 TI (...)
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| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
訂購和質(zhì)量
- RoHS
- REACH
- 器件標(biāo)識
- 引腳鍍層/焊球材料
- MSL 等級/回流焊峰值溫度
- MTBF/時基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測
- 制造廠地點(diǎn)
- 封裝廠地點(diǎn)