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DS90C383B

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+3.3V 可編程 LVDS 發送器 24 位平板顯示器 (FPD) 鏈路 - 65MHz

產品詳情

Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link LVDS Color depth (bpp) 24 Features Low-EMI Point-to-Point Communication Rating Catalog Operating temperature range (°C) -10 to 70
Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link LVDS Color depth (bpp) 24 Features Low-EMI Point-to-Point Communication Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 56 113.4 mm2 14 x 8.1
  • No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered
  • Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or -5% down spread
  • "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high
  • 18 to 68 MHz shift clock support
  • Best-in-Class Setup and Hold Times on TxINPUTs
  • Tx power consumption < 130 mW (typ) at 65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-down mode < 60μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow bus reduces cable size and cost
  • Up to 1.8 Gbps throughput
  • Up to 227 Megabytes/sec bandwidth
  • 345 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Compatible with TIA/EIA-644 LVDS standard
  • Low profile 56-lead TSSOP package
  • Improved replacement for:
    • SN75LVDS83, DS90C383A

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

  • No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered
  • Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or -5% down spread
  • "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high
  • 18 to 68 MHz shift clock support
  • Best-in-Class Setup and Hold Times on TxINPUTs
  • Tx power consumption < 130 mW (typ) at 65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-down mode < 60μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow bus reduces cable size and cost
  • Up to 1.8 Gbps throughput
  • Up to 227 Megabytes/sec bandwidth
  • 345 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Compatible with TIA/EIA-644 LVDS standard
  • Low profile 56-lead TSSOP package
  • Improved replacement for:
    • SN75LVDS83, DS90C383A

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

The DS90C383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90C383B transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90C383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90C383B transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
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類型 標題 下載最新的英語版本 日期
* 數據表 DS90C383B 3.3V Prog LVDS Trans 24-Bit FPD Link-65 MHz 數據表 (Rev. G) 2013年 4月 17日
應用手冊 High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018年 11月 9日
應用手冊 How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 2018年 6月 29日
應用手冊 AN-1032 An Introduction to FPD-Link (Rev. C) 2017年 8月 8日
應用手冊 Receiver Skew Margin for Channel Link I and FPD Link I Devices 2016年 1月 13日
應用手冊 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 2004年 5月 15日
應用手冊 AN-1056 STN Application Using FPD-Link 2004年 5月 14日
應用手冊 AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 2004年 5月 14日

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用戶指南: PDF
英語版 (Rev.A): PDF
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參考設計

TIDA-01051 — 針對自動測試設備優化 FPGA 利用率和數據吞吐量的參考設計

TIDA-01051 參考設計用于演示超高通道數的數據采集 (DAQ) 系統（如用在自動測試設備 (ATE) 中的系統）經過優化的通道密度、集成、功耗、時鐘分配和信號鏈性能。利用串行器（如 TI DS90C383B）將多個同步采樣 ADC 輸出與多個 LVDS 線路相結合，可顯著減少主機 FPGA 必須處理的引腳數量。? 因此，單個 FPGA 可處理的 DAQ 通道數量顯著增加，而且電路板布線的復雜度大幅降低。
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原理圖: PDF
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TSSOP (DGG) 56 Ultra Librarian

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  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
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  • 封裝廠地點

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