產品詳情

Bits (#) 6 Data rate (max) (Mbps) 24 Direction control (typ) Fixed-direction Vin (min) (V) 5 Vin (max) (V) 18 Vout (min) (V) 5 Vout (max) (V) 18 Applications GPIO Features High-voltage Prop delay (ns) 280 Technology family CD4000 Supply current (max) (mA) 5 Rating Military Operating temperature range (°C) -55 to 125
Bits (#) 6 Data rate (max) (Mbps) 24 Direction control (typ) Fixed-direction Vin (min) (V) 5 Vin (max) (V) 18 Vout (min) (V) 5 Vout (max) (V) 18 Applications GPIO Features High-voltage Prop delay (ns) 280 Technology family CD4000 Supply current (max) (mA) 5 Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 16 135.3552 mm2 19.56 x 6.92
  • Independence of power-supply sequence considerations - VCC can exceed VDD; input signals can exceed both VCC and VDD
  • Up and down level-shifting capability
  • Shiftable input threshold for either CMOS or TTL compatibility
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current @ 20 V
  • Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 5V, 10 V, and 15 V parametric ratings
  • Meets all requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor.
  • Independence of power-supply sequence considerations - VCC can exceed VDD; input signals can exceed both VCC and VDD
  • Up and down level-shifting capability
  • Shiftable input threshold for either CMOS or TTL compatibility
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current @ 20 V
  • Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 5V, 10 V, and 15 V parametric ratings
  • Meets all requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor.

CD4504B hex voltage level-shifter consists of six circuits which shift input signals from the VCC logic level to the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCC HIGH logic state. When the SELECT input is a LOW logic state, each circuit translates signals from one CMOS level to another.

The CD4504B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4504B hex voltage level-shifter consists of six circuits which shift input signals from the VCC logic level to the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCC HIGH logic state. When the SELECT input is a LOW logic state, each circuit translates signals from one CMOS level to another.

The CD4504B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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類型 標題 下載最新的英語版本 日期
* 數據表 CD4504B TYPES 數據表 (Rev. D) 2004年 11月 9日

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓