CD4017B

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具有 10 個(gè)解碼輸出的 CMOS 十進(jìn)制計(jì)數(shù)器

產(chǎn)品詳情

Function Counter Bits (#) 4 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Function Counter Bits (#) 4 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm2 19.3 x 9.4 SOIC (D) 16 59.4 mm2 9.9 x 6 SOP (NS) 16 79.56 mm2 10.2 x 7.8 TSSOP (PW) 16 32 mm2 5 x 6.4
  • Fully static operation
  • Medium speed operation…10 MHz (typ.) at VDD = 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Decade counter/decimal decode display (CD4017B)
    • Binary counter/decoder
    • Frequency division
    • Counter control/timers
    • Divde-by-N counting
    • For further application information, see ICAN-6166 "COS/MOS MSI Counter and Register Design and Applications"

  • Fully static operation
  • Medium speed operation…10 MHz (typ.) at VDD = 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Decade counter/decimal decode display (CD4017B)
    • Binary counter/decoder
    • Frequency division
    • Counter control/timers
    • Divde-by-N counting
    • For further application information, see ICAN-6166 "COS/MOS MSI Counter and Register Design and Applications"

CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.

These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT siganl is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes on cycle every 10 clock input cycles in the CD4017B or every 8 clock input cycles in the CD4022B and is used to ripple-clock the succeeding device in a multi-device counting chain.

The CD4017B and CD4022B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4017B types also are supplied in 16-lead small-outline packages (M and M96 suffixes).

CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.

These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT siganl is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes on cycle every 10 clock input cycles in the CD4017B or every 8 clock input cycles in the CD4022B and is used to ripple-clock the succeeding device in a multi-device counting chain.

The CD4017B and CD4022B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4017B types also are supplied in 16-lead small-outline packages (M and M96 suffixes).

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頂層文檔 類型 標(biāo)題 格式選項(xiàng) 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 CD4017B, CD4022B TYPES 數(shù)據(jù)表 (Rev. C) 2004年 2月 17日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 2025年 11月 13日
應(yīng)用手冊(cè) Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語(yǔ)版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應(yīng)用手冊(cè) Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用戶指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
應(yīng)用手冊(cè) Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日

設(shè)計(jì)與開發(fā)

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評(píng)估板

14-24-LOGIC-EVM — 采用 14 引腳至 24 引腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產(chǎn)品通用評(píng)估模塊

14-24-LOGIC-EVM 評(píng)估模塊 (EVM) 設(shè)計(jì)用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。

用戶指南: PDF | HTML
英語(yǔ)版 (Rev.B): PDF | HTML
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參考設(shè)計(jì)

PMP11112 — 6V-16V 輸入的四相交錯(cuò)同步升壓轉(zhuǎn)換器音頻放大器 (25V@24A) 參考設(shè)計(jì)

這款 600W 四相交錯(cuò)同步升壓轉(zhuǎn)換器,可從 6V-16V 輸入中提供 25V@24A 輸出。四相交錯(cuò)工作模式可減少輸入與輸出電容數(shù)量,并通過(guò)表面貼裝元件實(shí)現(xiàn)更優(yōu)的熱平衡。
測(cè)試報(bào)告: PDF
原理圖: PDF
參考設(shè)計(jì)

TIDA-00223 — 車用音頻 I2S 同軸 D 類放大器的參考設(shè)計(jì)

這款基于 I2S/TDM 的參考設(shè)計(jì)是光纖/模擬銅線的低成本易用型替代品,用于將汽車(聲音)控制面板連接到輸出級(jí)/功率放大器。它既支持 I2S,也支持 TDM,能夠?qū)?shù)字音頻信號(hào)傳輸至揚(yáng)聲器的 16 個(gè)獨(dú)立通道(各通道的功率輸出均為 80W/4?)。它也支持采用單一屏蔽雙絞線 (STP) 或同軸電纜通過(guò) I2C 與控制單元或處理器進(jìn)行雙向通信。此外,TIDA-00223 參考設(shè)計(jì)附帶電源,支持快速實(shí)施,并可滿足現(xiàn)代汽車對(duì)于保護(hù)和診斷功能的所有需求。
設(shè)計(jì)指南: PDF
原理圖: PDF
封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

訂購(gòu)和質(zhì)量

包含信息:
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息:
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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