產品詳情

Bits (#) 4 Data rate (max) (Mbps) 24 Direction control (typ) Fixed-direction Vin (min) (V) 3 Vin (max) (V) 18 Vout (min) (V) 3 Vout (max) (V) 18 Applications GPIO Features High-voltage Prop delay (ns) 600 Technology family CD4000 Supply current (max) (mA) 0.6 Rating Catalog Operating temperature range (°C) -55 to 125
Bits (#) 4 Data rate (max) (Mbps) 24 Direction control (typ) Fixed-direction Vin (min) (V) 3 Vin (max) (V) 18 Vout (min) (V) 3 Vout (max) (V) 18 Applications GPIO Features High-voltage Prop delay (ns) 600 Technology family CD4000 Supply current (max) (mA) 0.6 Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 16 181.42 mm2 19.3 x 9.4 SOP (NS) 16 79.56 mm2 10.2 x 7.8 TSSOP (PW) 16 32 mm2 5 x 6.4
  • Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD
  • Up and down level-shifting capability
  • Three-state outputs with separate enable controls
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range):
       = 1 V at VCC = 5 V, VDD = 10 V
       = 2 V at VCC = 10 V, VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
    • Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations

Data sheet acquired from Harris Semiconductor
  • Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD
  • Up and down level-shifting capability
  • Three-state outputs with separate enable controls
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range):
       = 1 V at VCC = 5 V, VDD = 10 V
       = 2 V at VCC = 10 V, VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
    • Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations

Data sheet acquired from Harris Semiconductor

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.

The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.

The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.

The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.

The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.

The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.

The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
下載 觀看帶字幕的視頻 視頻

您可能感興趣的相似產品

open-in-new 比較替代產品
功能與比較器件相似
TXH0137D-Q1 預發布 具有開漏輸出的汽車級、固定方向、7 位 30V 電壓電平轉換器 Automotive qualified and higher voltage range with open drain output

技術文檔

star =有關此產品的 TI 精選熱門文檔
未找到結果。請清除搜索并重試。
查看全部 15
類型 標題 下載最新的英語版本 日期
* 數據表 CD40109B TYPES 數據表 (Rev. B) 2003年 1月 15日
應用手冊 原理圖檢查清單 - 使用自動雙向轉換器進行設計的指南 PDF | HTML 英語版 PDF | HTML 2024年 12月 3日
應用手冊 原理圖檢查清單 - 使用固定或方向控制轉換器進行設計的指南 PDF | HTML 英語版 PDF | HTML 2024年 10月 3日
應用手冊 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
應用手冊 了解 CMOS 輸出緩沖器中的瞬態驅動強度與直流驅動強度 PDF | HTML 最新英語版本 (Rev.A) PDF | HTML 2024年 5月 15日
應用簡報 利用 TXH 實現高電壓電平轉換 PDF | HTML 英語版 PDF | HTML 2023年 10月 6日
選擇指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應用手冊 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應用手冊 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用戶指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
應用手冊 Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設計和開發

如需其他信息或資源，請點擊以下任一標題進入詳情頁面查看（如有）。

評估板

14-24-LOGIC-EVM — 采用 14 引腳至 24 引腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模塊

14-24-LOGIC-EVM 評估模塊 (EVM) 設計用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。

用戶指南: PDF | HTML
英語版 (Rev.B): PDF | HTML
TI.com 上無現貨
封裝 引腳 CAD 符號、封裝和 3D 模型
PDIP (N) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓

視頻