SLAS653C February 2010 – February 2017 TLV320AIC3120
PRODUCTION DATA.
- 1 Device Overview
- 2 Revision History
- 3 Device Comparison
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics
- 5.6 Power Dissipation Ratings
- 5.7 I2S, LJF, and RJF Timing in Master Mode
- 5.8 I2S, LJF, and RJF Timing in Slave Mode
- 5.9 DSP Timing in Master Mode
- 5.10 DSP Timing in Slave Mode
- 5.11 I2C Interface Timing
- 5.12 Typical Characteristics
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Power-Supply Sequence
- 7.3.2 Reset
- 7.3.3 Device Start-Up Lockout Times
- 7.3.4 PLL Start-Up
- 7.3.5 Power-Stage Reset
- 7.3.6 Software Power Down
- 7.3.7 Audio Analog I/O
- 7.3.8 miniDSP
- 7.3.9 Digital Processing Low-Power Modes
- 7.3.10
Audio ADC and Analog Inputs
- 7.3.10.1 MICBIAS and Microphone Preamplifier
- 7.3.10.2 Automatic Gain Control (AGC)
- 7.3.10.3 Delta-Sigma ADC
- 7.3.10.4
ADC Decimation Filtering and Signal Processing
- 7.3.10.4.1 ADC Processing Blocks
- 7.3.10.4.2
ADC Processing Blocks - Signal Chain Details
- 7.3.10.4.2.1 First-Order IIR, AGC, Filter A
- 7.3.10.4.2.2 Five Biquads, First-Order IIR, AGC, Filter A
- 7.3.10.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A
- 7.3.10.4.2.4 First-Order IIR, AGC, Filter B
- 7.3.10.4.2.5 Three Biquads, First-Order IIR, AGC, Filter B
- 7.3.10.4.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B
- 7.3.10.4.2.7 First-Order IIR, AGC, Filter C
- 7.3.10.4.2.8 Five Biquads, First-Order IIR, AGC, Filter C
- 7.3.10.4.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C
- 7.3.10.4.3 User-Programmable Filters
- 7.3.10.4.4 ADC Digital Decimation Filter Characteristics
- 7.3.10.4.5 ADC Data Interface
- 7.3.10.5 Updating ADC Digital Filter Coefficients During Record
- 7.3.10.6 Digital Microphone Function
- 7.3.10.7 DC Measurement
- 7.3.10.8 ADC Setup
- 7.3.11 Example Register Setup to Record Analog Data Through ADC to Digital Out
- 7.3.12
Audio DAC and Audio Analog Outputs
- 7.3.12.1
DAC
- 7.3.12.1.1 DAC Processing Blocks
- 7.3.12.1.2
DAC Processing Blocks — Signal Chain Details
- 7.3.12.1.2.1 Three Biquads, Filter A
- 7.3.12.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B
- 7.3.12.1.2.3 Six Biquads, First-Order IIR, Filter A or B
- 7.3.12.1.2.4 IIR, Filter B or C
- 7.3.12.1.2.5 Four Biquads, DRC, Filter B
- 7.3.12.1.2.6 Four Biquads, Filter B
- 7.3.12.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C
- 7.3.12.1.2.8 Four Biquads, First-Order IIR, Filter C
- 7.3.12.1.2.9 Five Biquads, DRC, Beep Generator, Filter A
- 7.3.12.1.3 DAC User-Programmable Filters
- 7.3.12.1.4 DAC Interpolation Filter Characteristics
- 7.3.12.2 DAC Digital-Volume Control
- 7.3.12.3 Volume Control Pin
- 7.3.12.4 Dynamic Range Compression
- 7.3.12.5 Headset Detection
- 7.3.12.6 Interrupts
- 7.3.12.7 Key-Click Functionality With Beep Generator (PRB_P25)
- 7.3.12.8 Programming DAC Digital Filter Coefficients
- 7.3.12.9 Updating DAC Digital Filter Coefficients During PLAY
- 7.3.12.10 Digital Mixing and Routing
- 7.3.12.11 Analog Audio Routing
- 7.3.12.12 Analog Outputs
- 7.3.12.13 Audio-Output Stage-Power Configurations
- 7.3.12.14 DAC Setup
- 7.3.12.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
- 7.3.12.1
DAC
- 7.3.13 CLOCK Generation and PLL
- 7.3.14 Timer
- 7.3.15 Digital Audio and Control Interface
- 7.4
Register Map
- 7.4.1 TLV320AIC3120 Register Map
- 7.4.2
Registers
- 7.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
- 7.4.2.2 Control Registers, Page 1: DAC and ADC Routing, PGA, Power-Controls, and MISC Logic-Related Programmability
- 7.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
- 7.4.2.4 Control Registers, Page 4: ADC Digital Filter Coefficients
- 7.4.2.5 Control Registers, Page 5: ADC Programmable Coefficients RAM (65:127)
- 7.4.2.6 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
- 7.4.2.7 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)
- 7.4.2.8 Control Registers, Page 10: DAC Programmable Coefficients RAM Buffer A (129:191)
- 7.4.2.9 Control Registers, Page 11: DAC Programmable Coefficients RAM Buffer A (193:255)
- 7.4.2.10 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)
- 7.4.2.11 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
- 7.4.2.12 Control Registers, Page 14: DAC Programmable Coefficients RAM Buffer B (129:191)
- 7.4.2.13 Control Registers, Page 15: DAC Programmable Coefficients RAM Buffer B (193:255)
- 7.4.2.14 Control Registers, Page 32: ADC DSP Engine Instruction RAM (0:31)
- 7.4.2.15 Control Registers, Pages 33-43: ADC DSP Engine Instruction RAM (32:63) Through (352:383)
- 7.4.2.16 Control Registers, Page 64: DAC DSP Engine Instruction RAM (0:31)
- 7.4.2.17 Control Registers, Pages 65 to 95: DAC DSP Engine Instruction RAM (32:63) Through (992:1023)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical Packaging and Orderable Information
Package Options
Mechanical Data (Package|Pins)
- RHB|32
Thermal pad, mechanical data (Package|Pins)
- RHB|32
Orderable Information
1 Device Overview
1.1 Features
- Mono Audio DAC With 95-dB SNR
- Mono Audio ADC With 90-dB SNR
- Supports 8-kHz to 192-kHz Separate DAC and ADC Sample Rates
- Instruction-Programmable Embedded miniDSP
- Mono Class-D BTL Speaker Driver (2.5 W Into 4 Ω or 1.6 W Into 8 Ω) Output
- Mono Headphone/Lineout Outputs
- One Differential or Three Single-Ended Inputs With Mixing and Level Control
- Microphone With Bias, Preamp PGA, and AGC
- Built-in Digital Audio Processing Blocks (PRB) With User-Programmable Biquad, FIR Filters, and DRC
- Bass Boost/Treble/EQ With up to Five Biquads for Record and up to Six Biquads for Playback
- Digital Mixing Capability
- Pin Control or Register Control for Digital Playback Volume Control Settings
- Programmble PLL for Flexible Clock Generation
- I2S, Left-Justified, Right-Justified, DSP, and TDM Audio Interfaces
- I2C Control With Register Auto-Increment
- Full Power-Down Control
- Power Supplies:
- Analog: 2.7 V–3.6 V
- Digital Core: 1.65 V–1.95 V
- Digital I/O: 1.1 V–3.6 V
- Class-D: 2.7 V–5.5V (SPKVDD ≥ AVDD)
- 5-mm × 5-mm 32-QFN Package
1.2 Applications
- Portable Audio Devices
- Mobile Internet Devices
- eBooks
- Adaptive Filtering Applications
1.3 Description
The TLV320AIC3120 device is a low-power, highly integrated, high-performance codec which features a mono audio DAC and mono audio ADC.
The TLV320AIC3120 device features a high-performance audio codec with 24-bit mono playback and mono record functionality. The device integrates several analog features, such as a microphone interface, headphone drivers, and speaker drivers. The TLV320AIC3120 device has a fully programmable miniDSP for digital audio processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, left-justified and right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ are supported by the programmable digital signal-processing blocks (PRB). An on-chip PLL provides the high-speed clock needed by the digital signal-processing block. The volume level is controlled either by pin control or by register control. The audio functions are controlled using the I2C serial bus.
The TLV320AIC3120 device is available in a 32-pin VQFN package.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TLV320AIC3120 | VQFN (32) | 5.00 mm × 5.00 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
1.4 Functional Block Diagram
