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SPRUIM6A October 2018 – November 2020

3.3.6.1 Gigabit Ethernet PHY Default Configuration

The default configuration of the DP83867 is determined using a number of resistor pull-up and pull-down values on specific pins of the PHY. Depending on the values installed, each of the configuration pins can be set to one of four modes by using the pull-up and pull-down options provided. The AM65x IDK uses the 48-pin QFN package, designated with the RGZ suffix, which only supports the RGMII interface.

The DP83867 PHY uses four level configurations based on resistor strapping, which generate four distinct voltage ranges. The resistors are connected to the RX data and control pins, which are normally driven by the PHY and are inputs to the processor. The voltage range for each mode is shown below:

Mode 1 - 0 V to 0.1764 V

Mode 2 – 0.252 V to 0.3438 V

Mode 3 – 0.405 V to 0.5112 V

Mode 4 – 1.2492 V to 1.5984 V

Default configurations of all phys are mentioned in Table 3-23.

Table 3-23 Default Strap Setting of Ethernet PHYs

	Signal	Mode	Default Configuration		Configuration	Description
	Signal	Mode	Pull Up	Pull Down	Configuration	Description
PRG2 RGMII1 PHY (J14A)	RX_D0	1	Open	Open	PHY_AD1 = 0 and PHY_AD0 = 0	Address of the PHY is set to 00000
	RX_D2	1	Open	Open	PHY_AD3 = 0 and PHY_AD2 = 0	Address of the PHY is set to 00000
	RX_DV/RX_CTRL	1	Open	Open	N/A	N/A
	LED_2	1	Open	Open	RGMII Clock Skew TX[1]=0 and RGMII Clock Skew TX[0]=0	RGMII Clock Skew TX = 2 ns and advertise
	LED_1	1	Open	Open	ANEG_SEL=0 and RGMII Clock Skew TX[1]=0	RGMII Clock Skew TX = 2 ns and advertise
	GPIO_0	1	Open	Open	RGMII Clock Skew RX[0]=0	RGMII Clock Skew RX = 2 ns
	GPIO_1	1	Open	Open	RGMII Clock Skew RX[2]=0 and RGMII Clock Skew RX[1]=0	RGMII Clock Skew RX = 2 ns
PRG2 RGMII1 PHY (J14B)	RX_D0	4	2.49K	Open	PHY_AD1 = 1 and PHY_AD0 = 1	Address of the PHY is set to 00011
	RX_D2	1	Open	Open	PHY_AD3 = 0 and PHY_AD2 = 0	Address of the PHY is set to 00011
	RX_DV/RX_CTRL	1	Open	Open	N/A	N/A
	LED_2	1	Open	Open	RGMII Clock Skew TX[1]=0 and RGMII Clock Skew TX[0]=0	RGMII Clock Skew TX = 2 ns and advertise
	LED_1	1	Open	Open	ANEG_SEL=0 and RGMII Clock Skew TX[1]=0	RGMII Clock Skew TX = 2 ns and advertise
	GPIO_0	1	Open	Open	RGMII Clock Skew RX[0]=0	RGMII Clock Skew RX = 2 ns
	GPIO_1	1	Open	Open	RGMII Clock Skew RX[2]=0 and RGMII Clock Skew RX[1]=0	RGMII Clock Skew RX = 2 ns
PRG2 RGMII1 PHY (J12)	RX_D0	1	Open	Open	PHY_AD1 = 0 and PHY_AD0 = 0	Address of the PHY is set to 00000
	RX_D2	1	Open	Open	PHY_AD3 = 0 and AN2 = 0	Address of the PHY is set to 00000
	RX_DV/RX_CTRL	1	Open	Open	N/A	N/A
	LED_2	1	Open	Open	RGMII Clock Skew TX[1]=0 and RGMII Clock Skew TX[0]=0	RGMII Clock Skew TX = 2 ns and advertise
	LED_1	1	Open	Open	ANEG_SEL=0 and RGMII Clock Skew TX[1]=0	RGMII Clock Skew TX = 2 ns and advertise
	GPIO_0	1	Open	Open	RGMII Clock Skew RX[0]=0	RGMII Clock Skew RX = 2 ns
	GPIO_1	1	Open	Open	RGMII Clock Skew RX[2]=0 and RGMII Clock Skew RX[1]=0	RGMII Clock Skew RX = 2 ns

Figure 3-16 Strapping Diagram for MCU and PRG2-RGMII1 Ethernets

Figure 3-17 Strapping Diagram for PRG2-RGMII2 Ethernet

Note:

Resistors which are highlighted in red color boxes are DNI components.