SPRABA5D January 2014 – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810
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Using the AM18xx Bootloader
- Trademarks
- 1 Introduction
- 2 Boot Modes
- 3 Non-AIS Boot Modes
- 4
Application Image Script (AIS) Boot
- 4.1 Section Load Command (0x58535901)
- 4.2 Section Fill Command (0x5853590A)
- 4.3 Enable CRC Command (0x58535903)
- 4.4 Disable CRC Command (0x58535904)
- 4.5 Validate CRC Command (0x58535902)
- 4.6 Jump & Close Command (0x58535906)
- 4.7 Jump Command (0x58535905)
- 4.8 Sequential Read Enable Command (0x58535963)
- 4.9 Function Execute Command (0x5853590D)
- 4.10 Boot Table Command (0x58535907)
- 5
AISgen: Tool to Generate Boot Script (AIS Image)
- 5.1 Installation
- 5.2 Getting Started
- 5.3
Generating AIS
- 5.3.1 Boot Mode and Boot Peripheral Setup
- 5.3.2 Phase-Locked Loop (PLL) Setup
- 5.3.3 Synchronous Dynamic Random Access Memory (SDRAM) Setup
- 5.3.4 DDR Setup
- 5.3.5 PSC Setup
- 5.3.6 Pin Multiplexing Setup
- 5.3.7 Application File Selection
- 5.3.8 AIS File Selection
- 5.3.9 Status and Messages
- 5.3.10 Additional AIS Options
- 5.3.11 Command Line Usage
- 6 Master Boot – Booting From a Slave Memory Device
- 7 Slave Boot – Booting From an External Master Host
- 8 UART Boot Host - Using Your PC as a UART Boot Master
- 9 Boot Requirements, Constraints and Default Settings
- 10 References
- A Boot Mode Selection Table
- B Details of Supported NAND Devices
- C CRC Computation Algorithm
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D Details of Pre-Defined ROM Functions
- D.1 PLL0 Configuration (Index = 0, Argument Count = 2)
- D.2 PLL1 Configuration (Index = 1, Argument Count = 2)
- D.3 Clock Configuration (Index = 2, Argument Count = 1)
- D.4 mDDR/DDR2 Controller Configuration (Index = 3, Argument Count = 8)
- D.5 EMIFA SDRAM Configuration (Index = 4, Argument Count = 5)
- D.6 EMIFA Async Configuration (Index = 5, Argument Count = 5)
- D.7 PLL and Clock Configuration (Index = 6, Argument Count = 3)
- D.8 Power and Sleep Configuration (PSC) (Index = 7, Argument Count = 1)
- D.9 Pinmux Configuration (Index = 8, Argument Count = 3)
- E ROM Revision History
- Revision History
9.3 I2C-Boot Modes
- Default clocks: For I2C and SPI master-boot modes and UART-boot modes, the bootloader applies default peripheral clocks settings as shown in Table 6:
- All I2C Modes: The I2C bus must use 7-bit addressing.
- When booting from I2C0 in slave mode, the input clock source must be in the 21.0 MHz – 36.0 MHz range.
- The bootloader must be addressed with the I2C slave address 0x28.
- When booting from I2C1 in slave mode, the input clock source must be in the 16.8 MHz – 30.0 MHz range. In this boot mode, the bootloader initializes the PLL0 with the following parameters and takes it out of the default bypass mode. This is required to set the I2C1 module clock to a valid range.
- The bootloader must be addressed with the I2C slave address 0x29.
- The EEPROM must respond to the I2C slave address 0x50. The bootloader will look for an AIS image at offset 0x00000000.
Table 8. Default PLL Configuration in I2C1 Slave-Boot Mode
| Div/Mul | Value | Clock | Freq Assuming
24 MHz Input |
Freq Assuming
25 MHz Input |
|---|---|---|---|---|
| PREDIV | /1 | |||
| PLLM | *20 | |||
| POSTDIV | /2 | |||
| PLLDIV1 | /1 | SYSCLK1 | 240 | 250 |
| PLLDIV2 | /2 | SYSCLK2 | 120 | 125 |
| PLLDIV3 | /4 | SYSCLK3 | 60 | 62.5 |
| PLLDIV4 | /4 | SYSCLK4 | 60 | 62.5 |
| PLLDIV6 | /1 | SYSCLK6 | 240 | 250 |
| PLLDIV7 | /5 | SYSCLK7 | 48 | 50 |
Figure 26. I2C SDA Signal Diagram for I2C EEPROM Boot (with sequential read enabled)