SPRABA5D January 2014 – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810
The EMIFA SDRAM configuration function configures the EMIFA registers responsible for SDRAM timing and configuration.
| 31 | 0 | ||
| Arg1 | SDCR | ||
| Arg2 | SDTIMR | ||
| Arg3 | SDSRETR | ||
| Arg4 | SDRCR | ||
| Arg5 | DIV4p5_CLK_EN | ||
This first four function arguments are written directly to the EMIFA registers with the same names.
The DIV4p5_CLK_EN is a Boolean value to enable the use of the 4.5 divider of the PLL0 multiplier output as the input clock to the EMIFA peripheral.
Before programming EMIFA registers, this function applies the necessary PINMUX for 16- or 32-bit SDRAM access (based on the value of the SDCR register) and wakes up the EMIFA peripheral from its default reset state.