SNVU799 March 2022 LP87523-Q1
This technical reference manual can be used as a reference for the LP875230C-Q1 default register bits after OTP memory download. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8752x-Q1 Four-Phase 10-A Buck Converter With Integrated Switches data sheet
Table 1-1 lists the main OTP settings for power rails. Table 2-1 lists the register bits loaded from OTP memory.
| Description | Bit Name | LP875230CRNFRQ1 Value | |
|---|---|---|---|
| Device identification | OTP configuration | OTP_ID | 7Eh |
| BUCK0, BUCK1 (2-phase operation) | Output voltage | BUCK0_VSET | 850 mV |
| Enable, EN pin, or I2C register | EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECT | EN1 | |
| Force PWM | BUCK0_FPWM | Yes | |
| Force multiphase | BUCK0_FPWM_MP | Yes | |
| Peak current limit per phase | N/A | 4 A | |
| Maximum load current | N/A | 6 A | |
| Slew rate | N/A | 3.8 mV/μs | |
| BUCK2 | Output voltage | BUCK2_VSET | 1100 mV |
| Enable, EN pin, or I2C register | EN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECT | EN1 | |
| Force PWM | BUCK2_FPWM | Yes | |
| Peak current limit | N/A | 3 A | |
| Maximum load current | N/A | 2 A | |
| Slew rate | N/A | 3.8 mV/μs | |
| BUCK3 | Output voltage | BUCK3_VSET | 1800 mV |
| Enable, EN pin, or I2C register | EN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECT | EN1 | |
| Force PWM | BUCK3_FPWM | Yes | |
| Peak current limit | N/A | 3 A | |
| Maximum load current | N/A | 2 A | |
| Slew rate | N/A | 3.8 mV/μs | |
| Switching frequency | N/A | 2 MHz | |
| I2C address | N/A | 61h | |
The maximum total output capacitance (local + POL) per phase (BUCK0, BUCK1, BUCK2, and BUCK3) depends on the slew rate setting. Check the data sheet for the allowed capacitance value.