1.1 FDC2x1x Operational Parameters That Affect Duty Cycling

The FDC family of devices are either 2 or 4 channel devices. When configured to sample on more than one channel, the FDC sequentially samples the channels. Figure 1 and Figure 2 show both single channel and multichannel mode sequencing in continuous conversion of the FDC2x1x, representing a non-duty cycled mode of operation. The normal sequence of tasks on each channel include sensor activation, conversion, channel switching (multi-mode only), and data readback.

The sum of the times it takes for each task to complete is equivalent to a sample time, during which the device needs to be actively running. In the data sheet, this is referred to as normal mode, but throughout this application note this will be referred to as active mode. We will also distinguish between sampling period (T_S) and sampling time (t_N). The former is defined as the time between consecutive samples on the same channel, and the latter is defined as the time required to obtain a single sample. The latter is expressed in Equation 1.

In general, t_SD < t_S << t_C. Consequently, t_C has the most impact on sampling time and hence, duty cycle.

The sensor activation time, t_S, refers to the amount of time needed for the sensor oscillation to startup and stabilize. This activation time (t_S) is programmable through the SETTLECOUNT register for each channel and given by Equation 2 where f_REF is the reference clock frequency.

The sensor conversion time, t_C, is the largest part of this sequence. It represents the number of reference clock cycles (RCOUNT*16) used to perform a measurement conversion. As seen in Equation 3, the sensor conversion time can be set by the RCOUNT register value for each channel.

The choice of RCOUNT value is driven by the resolution required by the application. If the required resolution is N bits, then the following equation can be used to calculate an initial value for RCOUNT.

See section 9.3.2 of the data sheet (SNOSCZ5) for more explanation of RCOUNT and sample resolution.

When the FDC2x1x is in multichannel mode, the channel switch delay needs to be included in the total sampling time. This is the delay time between the end of a sensor conversion on one channel and the beginning of sensor activation on a subsequent channel. This delay time is relatively minimal and is given by Equation 5.

In addition to the time required to complete the three tasks discussed above, the microprocessor takes some time to read back the channel measurement. This data readback time, t_RB, is a function of the data resolution, the number of data registers being read, the number of clocking cycles to read or write to each register, and the I²C data rate.

The total time to complete this sequence is the total amount of time for which the FDC2x1x must be in active mode (Equation 1). If f_S is the required sampling rate and T_S is the sampling period (T_S=1/f_S), the idea behind the duty-cycling technique is that the device is put into sleep mode when it is not operating in this data conversion process (T_SLEEP = T_S – t_N). Consequently, the percentage of time the FDC is in a low power sleep mode is given by Equation 6.

For more information on how to configure the FDC2x1x, refer to the data sheet (SNOSCZ5).

In summary, given a minimum sampling rate required by the application, the duty cycle only needs to be large enough to meet the minimum resolution requirements of the application. Figure 3 illustrates this graphically.

To place the FDC in sleep mode, write the value 1 to the CONFIG.SLEEP_MODE_EN register field. While in sleep mode, the FDC retains its register contents except for that in the data registers, which must be read before the device is placed in sleep mode. To exit sleep mode, write the value 0 to the CONFIG.SLEEP_MODE_EN register field.