SNAU319 August 2025 LMK3H2108
| OTP Page | OUT0 (MHz) | OUT1 (MHz) | OUT2 (MHz) | OUT3 (MHz) | OUT4 (MHz) | OUT5 (MHz) | OUT6 (MHz) | OUT7 (MHz) |
|---|---|---|---|---|---|---|---|---|
| OTP Page 0 | 100 | 100 | 100 | 100 | 100 | 100 | 100 | 100 |
| OTP Page 1 | 100 | 100 | 100 | 100 | 100 | 100 | 100 | 100 |
| OTP Page 2 | 100 | 100 | 100 | 100 | 100 | 100 | 100 | 100 |
| OTP Page 3 | 100 | 100 | 100 | 100 | 100 | 100 | 100 | 100 |
| OTP Page | I2C Configuration |
|---|---|
| OTP Page 0 |
I2C Address: 0x68 1 Byte Register Addressing |
| OTP Page 1 |
I2C Address: 0x68 1 Byte Register Addressing |
| OTP Page 2 |
I2C Address: 0x68 1 Byte Register Addressing |
| OTP Page 3 |
I2C Address: 0x68 1 Byte Register Addressing |
| GPI Pin | Pin Behavior | Polarity | Internal Pull-Down | Internal Pull-Up |
|---|---|---|---|---|
| GPI0 | GPI | Normal | Disabled | Disabled |
| GPI1 | GPI | Normal | Disabled | Disabled |
| GPI2 | Group OE, OE_GROUP_2 | Inverted | Enabled | Disabled |
| GPI3 | Group OE, OE_GROUP_3 | Inverted | Enabled | Disabled |
| GPI4 | Group OE, OE_GROUP_4 | Inverted | Enabled | Disabled |
| GPI5 | Group OE, OE_GROUP_5 | Inverted | Enabled | Disabled |
| GPIO Pin | Pin Behavior | Polarity | Internal Pull-Down | Internal Pull-Up |
|---|---|---|---|---|
| GPIO0 | Dynamic OTP | Normal | Enabled | Disabled |
| GPIO1 | Dynamic OTP | Normal | Enabled | Disabled |
| GPIO2 | Group OE, OE_GROUP_8 | Inverted | Enabled | Disabled |
| GPIO3 | Group OE, OE_GROUP_9 | Inverted | Enabled | Disabled |
| GPIO4 | Group OE, OE_GROUP_10 | Inverted | Enabled | Disabled |
| Input | Powered Up/Down | Input Format | Input Termination |
|---|---|---|---|
| IN_0 | Powered Down | N/A (IN0 Unused) | None, DC |
| IN_1 | Powered Down | N/A (IN1 Unused) | None, DC |
| IN_2 | Powered Down | N/A (IN2 Unused) | None, DC |
| Output | Frequency (MHz) | Format | Clock Source | Output State | OE Group | SSC Behavior |
|---|---|---|---|---|---|---|
| OUT0 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | No OE Group | Disabled |
| OUT1 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_2 | Disabled |
| OUT2 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_3 | Disabled |
| OUT3 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_4 | Disabled |
| OUT4 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_5 | Disabled |
| OUT5 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_8 | Disabled |
| OUT6 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_9 | Disabled |
| OUT7 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_10 | Disabled |
| GPI Pin | Pin Behavior | Polarity | Internal Pull-Down | Internal Pull-Up |
|---|---|---|---|---|
| GPI0 | GPI | Normal | Disabled | Disabled |
| GPI1 | GPI | Normal | Disabled | Disabled |
| GPI2 | Group OE, OE_GROUP_2 | Inverted | Enabled | Disabled |
| GPI3 | Group OE, OE_GROUP_3 | Inverted | Enabled | Disabled |
| GPI4 | Group OE, OE_GROUP_4 | Inverted | Enabled | Disabled |
| GPI5 | Group OE, OE_GROUP_5 | Inverted | Enabled | Disabled |
| GPIO Pin | Pin Behavior | Polarity | Internal Pull-Down | Internal Pull-Up |
|---|---|---|---|---|
| GPIO0 | Dynamic OTP | Normal | Enabled | Disabled |
| GPIO1 | Dynamic OTP | Normal | Enabled | Disabled |
| GPIO2 | Group OE, OE_GROUP_8 | Inverted | Enabled | Disabled |
| GPIO3 | Group OE, OE_GROUP_9 | Inverted | Enabled | Disabled |
| GPIO4 | Group OE, OE_GROUP_10 | Inverted | Enabled | Disabled |
| Input | Powered Up/Down | Input Format | Input Termination |
|---|---|---|---|
| IN_0 | Powered Down | N/A (IN0 Unused) | None, DC |
| IN_1 | Powered Down | N/A (IN1 Unused) | None, DC |
| IN_2 | Powered Down | N/A (IN2 Unused) | None, DC |
| Output | Frequency (MHz) | Format | Clock Source | Output State | OE Group | SSC Behavior |
|---|---|---|---|---|---|---|
| OUT0 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | No OE Group | Enabled, -0.1% Down-spread |
| OUT1 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_2 | Enabled, -0.1% Down-spread |
| OUT2 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_3 | Enabled, -0.1% Down-spread |
| OUT3 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_4 | Enabled, -0.1% Down-spread |
| OUT4 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_5 | Enabled, -0.1% Down-spread |
| OUT5 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_8 | Enabled, -0.1% Down-spread |
| OUT6 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_9 | Enabled, -0.1% Down-spread |
| OUT7 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_10 | Enabled, -0.1% Down-spread |
| GPI Pin | Pin Behavior | Polarity | Internal Pull-Down | Internal Pull-Up |
|---|---|---|---|---|
| GPI0 | GPI | Normal | Disabled | Disabled |
| GPI1 | GPI | Normal | Disabled | Disabled |
| GPI2 | Group OE, OE_GROUP_2 | Inverted | Enabled | Disabled |
| GPI3 | Group OE, OE_GROUP_3 | Inverted | Enabled | Disabled |
| GPI4 | Group OE, OE_GROUP_4 | Inverted | Enabled | Disabled |
| GPI5 | Group OE, OE_GROUP_5 | Inverted | Enabled | Disabled |
| GPIO Pin | Pin Behavior | Polarity | Internal Pull-Down | Internal Pull-Up |
|---|---|---|---|---|
| GPIO0 | Dynamic OTP | Normal | Enabled | Disabled |
| GPIO1 | Dynamic OTP | Normal | Enabled | Disabled |
| GPIO2 | Group OE, OE_GROUP_8 | Inverted | Enabled | Disabled |
| GPIO3 | Group OE, OE_GROUP_9 | Inverted | Enabled | Disabled |
| GPIO4 | Group OE, OE_GROUP_10 | Inverted | Enabled | Disabled |
| Input | Powered Up/Down | Input Format | Input Termination |
|---|---|---|---|
| IN_0 | Powered Down | N/A (IN0 Unused) | None, DC |
| IN_1 | Powered Down | N/A (IN1 Unused) | None, DC |
| IN_2 | Powered Down | N/A (IN2 Unused) | None, DC |
| Output | Frequency (MHz) | Format | Clock Source | Output State | OE Group | SSC Behavior |
|---|---|---|---|---|---|---|
| OUT0 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | No OE Group | Enabled, -0.3% Down-spread |
| OUT1 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_2 | Enabled, -0.3% Down-spread |
| OUT2 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_3 | Enabled, -0.3% Down-spread |
| OUT3 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_4 | Enabled, -0.3% Down-spread |
| OUT4 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_5 | Enabled, -0.3% Down-spread |
| OUT5 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_8 | Enabled, -0.3% Down-spread |
| OUT6 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_9 | Enabled, -0.3% Down-spread |
| OUT7 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_10 | Enabled, -0.3% Down-spread |
| GPI Pin | Pin Behavior | Polarity | Internal Pull-Down | Internal Pull-Up |
|---|---|---|---|---|
| GPI0 | GPI | Normal | Disabled | Disabled |
| GPI1 | GPI | Normal | Disabled | Disabled |
| GPI2 | Group OE, OE_GROUP_2 | Inverted | Enabled | Disabled |
| GPI3 | Group OE, OE_GROUP_3 | Inverted | Enabled | Disabled |
| GPI4 | Group OE, OE_GROUP_4 | Inverted | Enabled | Disabled |
| GPI5 | Group OE, OE_GROUP_5 | Inverted | Enabled | Disabled |
| GPIO Pin | Pin Behavior | Polarity | Internal Pull-Down | Internal Pull-Up |
|---|---|---|---|---|
| GPIO0 | Dynamic OTP | Normal | Enabled | Disabled |
| GPIO1 | Dynamic OTP | Normal | Enabled | Disabled |
| GPIO2 | Group OE, OE_GROUP_8 | Inverted | Enabled | Disabled |
| GPIO3 | Group OE, OE_GROUP_9 | Inverted | Enabled | Disabled |
| GPIO4 | Group OE, OE_GROUP_10 | Inverted | Enabled | Disabled |
| Input | Powered Up/Down | Input Format | Input Termination |
|---|---|---|---|
| IN_0 | Powered Down | N/A (IN0 Unused) | None, DC |
| IN_1 | Powered Down | N/A (IN1 Unused) | None, DC |
| IN_2 | Powered Down | N/A (IN2 Unused) | None, DC |
| Output | Frequency (MHz) | Format | Clock Source | Output State | OE Group | SSC Behavior |
|---|---|---|---|---|---|---|
| OUT0 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | No OE Group | Enabled, -0.5% Down-spread |
| OUT1 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_2 | Enabled, -0.5% Down-spread |
| OUT2 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_3 | Enabled, -0.5% Down-spread |
| OUT3 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_4 | Enabled, -0.5% Down-spread |
| OUT4 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_5 | Enabled, -0.5% Down-spread |
| OUT5 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_8 | Enabled, -0.5% Down-spread |
| OUT6 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_9 | Enabled, -0.5% Down-spread |
| OUT7 | 100 | 100 Ω LP-HCSL | PATH1 | Enabled | OE_GROUP_10 | Enabled, -0.5% Down-spread |