SNAA345 December 2020 LMK5C33216
7.2 Holdover G.8262 Option 2
To meet this specification, a PLL in holdover must meet the requirements in Table 7-1 (Table 15 in the G.8262 specification). The procedure for this test is that the DUT obtains lock from IN0, which contains a valid input clock. Then the input is switched to IN1, which contains no valid input, thus entering holdover and remains in holdover for the remainder of the test. The LMK5C33216 met this specification. The TIE plot shown in Figure 7-2 demonstrates compliance to the standard in green.
| EEC Option 2 | |
|---|---|
| Applies For | S > TBD(6) |
| a1 (ns/s)(1) | 50 |
| a2 (ns/s)(2) | 300 |
| b (ns/s2)(3) | 4.63 × 10-4 |
| c (ns)(4) | 1000 |
| d (ns/s2)(5) | 4.63 × 10-4 |
Figure 7-2 Holdover
Option 2 Result