2 Synchronicity

An SPI primarily uses three interface lines:

• An interface clock initiated by the master device to ensure synchronous data transfers
• A data line for data sent from the master to a slave
• A data line for data sent from a slave to the master

A fourth wire that carries what is known as the slave- select signal is not required for controlling interface flow but is needed for addressing a specific slave out of a range of slave devices. Figure 1(a) shows a simplified schematic of a microcontroller unit (MCU) operating as the master that controls two data converters representing the slaves.

With byte lengths ranging from 8 to 12 bits and multiples, thereof, and data rates ranging from 1 to 20 Mbps, the standard SPI configuration allows for short propagation times and hence only short distances in order to maintain synchronicity between the interface clock and the data transmitted in both directions. Figure 1(b) shows the inter- face timing of the first three data bits when the SPI is configured to change data at the rising clock edge and to sample data at the falling clock edge.

Over long distances, however, the transmission cable introduces significant propagation delay into the signal path. Assuming a typical signal velocity of 5 ns/m, a 100-m cable will cause a propagation delay of 500 ns. Because the data sent from the master to the slave experiences the same delay as the master-initiated interface clock, both will remain in sync across the entire data link. In the opposite direction, however, the slave sends data to the master only when the first clock edge reaches the slave. Furthermore, this data will experience a second delay on its way back to the master, so the slave data will be out of sync by twice the cable’s propagation delay.

Of course, communicating across a 100-m cable won’t be possible without appropriate line drivers and receivers. These components will further increase the propagation delay by about another 50 ns, for a total of 550 ns. The slave data will therefore lag behind the first clock edge by a total of 1100 ns, or 11 bits when a data rate of 10 Mbps is assumed.

The only possible solution for restoring synchronicity between the slave data and the interface clock while maintaining a high data rate is to feed the clock signal from the slave back to the master. Figure 2 clarifies the benefit of clock feedback. Here to represents the first rising clock edge, or the start of a data transmission, and t_P is the data-link propagation delay. After traversing the data link, both the master clock (SCK_M) and the master data (MOSI) remain in sync. Feeding back the master clock signal synchronizes the clock with the slave data so that both arrive equally delayed at the master. The only requirement is that the master provide two independent SPI ports, one configured as a master (SPI1) and the other configured as a slave (SPI2). Most modern microcontrollers possess two or more SPI ports, so this requirement poses no problem.

Nevertheless, implementing a long-distance, SPI-compatible interface in the real world is not a trivial task. Long-distance data links are always subject to external noise sources, ground-potential differences (GPDs), volt- age and current surges due to inductive load switching, and often even reflections due to wrong or no termination. The flowing schematic in Figure 3 tries to cover all of these aspects by showcasing the various transceiver and protection circuits that can counteract the derogating effects.