SLVUDF7 October 2025
2.3 Power-Supply Connections
The PGA848EVM uses two sets of voltage supplies: input stage and output stage. The device operates using input-stage power supplies from ±4V (8V) to ±18V (36V) and output-stage power supplies from ±2.25V (4.5V) to ±18V (36V). The output-stage supply voltage must not exceed the input-stage supply voltage.
The input-stage power-supply connections for the PGA848EVM are provided through connector J13 at the top of the EVM. The input-stage positive power-supply connection is labeled +VCC, the negative power-supply connection is labeled –VEE, and the ground connection is labeled GND. To connect power to the PGA848EVM, insert wires into each terminal of J13 and then tighten the screws to make the connection.
Figure 2-4 Input Stage Power Supply Connector
(J13)Table 2-4 summarizes the pin definition for supply connector J13 and the allowed voltage range for each supply connection.
| Connector Pin Number | Supply Connection | Voltage Range |
|---|---|---|
| J13.3 | Input-stage positive supply (+VCC) | Single supply, VS = +VCC: 8V to 36V Dual supply, VS = (+VCC) – (–VEE): 4V to 18V |
| J13.2 | Ground | 0V |
| J13.1 | Negative supply (–VEE) | Single supply, VS = +VCC: 0V (GND) Dual supply, VS = (+VCC) – (–VEE): –4V to –18V |
| J14.1 | LVDD+_ext | Single supply, LVDD+_ext: 4.5V to 36V Dual supply, output stage supply (LVSS+) – (LVSS–): 2.25V to 18V |
| J14.2 | Ground | 0V |
| J14.3 | LVSS–_ext | Single supply, LVSS–_ext: 0V (GND) Dual supply, output stage supply (LVSS+) – (LVSS–): –2.25V to –18V |
| J14.4 | Ground | 0V |
By default, the output-stage supply-voltage levels (+LVDD and –LVSS) are set to the PGA848 positive (+VCC) and negative (–VEE) supplies, respectively. The +LVDD pin is connected to +VCC through jumper J9 1-2, and the –LVSS pin is connected to –VEE through J16 1-2. Screw terminal connector J14 provides access to the output-stage supply pins. To set the voltage level of LVDD and LVSS with an external supply, shunt jumper J9 2-3 to access the +LVDD using connector J14.1. In a similar fashion, shunt jumper J16 2-3 to access the –LVSS pin using connector J14.3.
Figure 2-5 Output Stage Power Supply Connector
(J14)Figure 2-6 shows the PGA848EVM voltage supply connections.
Figure 2-6 PGA848EVM Voltage Supply Connections