The board layout for the TPS54550EVM-158 is shown in Figure 5-1 through Figure 5-3. The topside layer of the TPS54550EVM-158 is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper.

The top layer contains the main power traces for VIN, OUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS54550 and a large area filled with ground. The bottom layer contains ground and some signal routing. The top and bottom and internal ground traces are connected with multiple vias placed around the board including four vias directly under the TPS54550 device to provide a thermal path from the PowerPAD? land to ground.

The input decoupling capacitor (C1) and bootstrap capacitor (C3) are all located as close to the IC as possible. In addition, the voltage setpoint resistor divider components are also kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, adjacent to the output capacitor C3.

Figure 5-1 Top-Side Layout

Figure 5-3 Top-Side Assembly

Figure 5-2 Bottom-Side Layout (Looking From Top Side)