The TPS7H5003-SP QMLP is a single output radiation-hardness-assured PWM controller that contains an integrated synchronous rectification output, optimized for DC-DC converters in space applications. The dead time and leading edge blank time are fixed at 50 ns for this device. The controller can be configured for maximum duty cycle of 75% or 100%. As such, the DCL pin can be left floating or connected to VLDO. Connection of the DCL pin to AVSS is not permissible for this device. The 0.613V ±1% accurate internal reference allows design of high-current buck converters for FPGA core voltages.

The TPS7H5003-SP QMLP can be driven using an external clock through the SYNC pin or run using the internal oscillator at a frequency programmed by the user. Other programmable features include the UVLO threshold, soft start, and slope compensation. The TPS7H5003-SP QMLP is packaged in a very small 24-pin TSSOP (thin-shrink small outline package) package.