4 Common Issues

This section lists some common issues that happen often, and includes a quick discussion about the potential causes. Sometimes unique issues present themselves as a common problem, so the causes discussed here are not necessarily an exhaustive list.

• When power is applied, the VCC waveform looks like a triangle wave. If the gate is probed, it is switching momentarily, but then shuts off.
  • The usual cause for this is that there is not enough effective capacitance on the board on VCC. ACF designs that use the TPS2375x family might require more capacitance. Small capacitors, such as 0603 size, have a smaller effective capacitance than a 0805 or 1206. Additionally, the voltage rating is important to check. If there is anything connected to VCC (or VB), then the amount of capacitance might need to be increased. Therefore, it is recommended to increase the capacitance on the VCC line.
  • Check that there is a small bypass capacitor on VCC.
  • The VCC cap has to power the design until the output is ramped up, so if the output takes too long to settle then the VCC cap can be drained. If there is too much output capacitance it can take too long to charge. Additionally, the secondary soft-start circuit could be taking too long. The solutions here is to reduce the output capacitance or reduce the capacitor in the secondary soft-start circuit.
• If the gate is not switching at the expected duty cycle when VCC is past its threshold, then the IC could be damaged or it could be something in the feedback. If the optocoupler is damaged, it could be pulling the feedback low. The feed-forward resistor could be putting too much bias on CS – the solution is to increase the resistance. The CS resistor or slope compensation could be incorrect. Sometimes adding a 47-pF capacitor in series with the slope compensation resistor can help filter this signal and make the difference.
• If a successful PoE negotiation is observed, but VSS and RTN do not go to 0 V, then the internal pass MOSFET could be damaged. This is often caused by ESD and surge events. Both of these events are system-level considerations, so there are a number of components and system parameters to be considered. TI recommends adding a TVS between VSS and RTN. This helps protect the IC during surge and ESD events. Additionally, reducing the common-mode capacitance helps with surge events. Besides MOSFET damage, the rise time of VDD_VSS needs to be checked. Ensure the PSE ramp-up time is compliant with the IEEE802.3 standard.
• If the output voltage changes with load, there are a few things that could be causing it:
  • The CS threshold is met before it should be
  • The feedback system either does not have enough gain margin, phase margin, or something is installed improperly (broken or incorrect part)
  • The shunt voltage regulator has the incorrect reference voltage. Check the part number for this.
  • The optocoupler could have the wrong CTR: look for 80%–160% or 100%–200%, or the optocoupler biasing current could be incorrect.
  • The timing of the circuit (especially ACFs) is off
• If a MOSFET is breaking, then it could be for the following reasons:
  • The switching voltage is too high. Example, the overshoot on Vds is 60 V and the MOSFET is rated for 40 V. This could be because there is no snubber, the snubber is the incorrect value, or the physical placement is too far away. The overshoot voltage can happen exclusively during start-up, shutdown, or during normal operation. Check all of these conditions.
  • Too high of peak currents. Check the transformer inductance and turns ratios as compared to a validated design (EVM or reference design). Also check the polarity (dots) of the transformer and ensure the polarity is correct.
  • Shoot-through, which is defined as when both the primary and secondary MOSFETs are ON at the same time. This is not possible in a diode flyback, but can happen in synchronous flybacks or ACFs. Shoot-through can cause a higher Vds, and more importantly it heats up the FET. Many times the issue is that the GATE of the synchronous (secondary) MOSFET is not turning off fast enough. The MOSFET could also need a faster diode across Vds. Sometimes no diode is present, which means the circuit is running off the body diode of the MOSFET. This body diode may not be fast enough for the switching frequency, so adding a faster diode can correct this. Another common cause here is that the gate charge of the MOSFET is too high. Please compare the current design to a known working design, such as an EVM or TI reference design. Compare the MOSFET gate charge and ensure the gate charge is not excessively larger. To check for shoot-through, capture both GATEs and DRAINS of the MOSFETs on the same oscilloscope shot.
    Note: Snubbers and diodes are not effective if they are placed too far away from what they are protecting. The distance creates a parasitic inductance that renders the diodes ineffective at their clamping voltage. This is also true of TVS diodes. Therefore, place the snubbers closer to the MOSFETs.

• If there is no successful PoE negotiation, the following are common causes:
  • The DEN is incorrect and must be adjusted properly for the input bridge type. A discrete diode bridge typically works with 24.9 k?. However, hybrid bridges, full MOSFET bridges or an integrated solution can have a lower resistance and therefore the resistor needs to increase. The resistor is typically in the 25 k? to 27 k? range.
  • The terminations of the input transformer, the Ethernet PHY, is incorrect.
  • The input capacitance between VDD_VSS is too high. The IEEE802.3 standard permits only 120 nF. Considering most ICs require a 0.1-μF bypass capacitor for VDD_VSS, the input filtering capacitors become limited.
  • If there is any added circuitry (like sensing) this can corrupt the detection current. Try removing this circuitry.
  • A component in the input rectification bridge is broken
  • Potentially the IC could be damaged and not producing the detection or class currents.

• If the PSE cuts off power after 500 ms or so, this is due to the MPS signal not being met. The IEEE802.3 standard has a minimal Maintain Power Signature (MPS) signal that needs to be sent to the PSE at about 10 mA. Many times, during the first power up of the board, there is no load attached to the output. Some designs do not draw this much current when there is no load attached. This is more common in diode flybacks since they can more easily slip into discontinuous conduction mode (DCM), which significantly drops the overall input current. Try adding some load to the output of the design to get the input current beyond the MPS signal minimum. This behavior is characterized by a successful PoE handshake and power-up, but after 500 ms or so the input power is cut off and the output drops as well. This behavior is usually the MPS signal.

• There are a few reasons for VCC damage. The first thing to check is VCC during shutdown. If there is an overvoltage, it can be caused by a number of factors. Read the Soft-Stop: TPS2373X Feature Explanation application note that discusses this situation at length. Common fixes include:
  • Increasing the amount of capacitance on VCC
  • Changing the amount of input bulk capacitance
  • Changing the amount of output bulk capacitance
  • Overvoltage on the MOSFETs in the design
  • The transformer can be the cause of this, so switching transformers to one used in an EVM or reference design
  • If the inductor on VCC is not big enough it can cause peak charging in ACF topologies, so increase the inductor
  • In a flyback, if the series resistor on VCC is not large enough, it can cause peak charging
  • If there is an error in the feedback, the output voltage can fly up which can cause VCC to also fly up and damage. Check the feedback components and compare them to a reference design
• The following are common causes for a break after a design works for a long time (hours, days, weeks):
  • Thermal issues are the most common cause for a break here. Electrical issues typically reveal themselves very quickly. Thermal issues can take a long time to show. Often the thermal issue is not every deployed device, but is a number of devices.
  • The next most common cause for breaking is a surge or ESD event. Again, electrical issues typically break the design early, but a design could operate without an ESD or surge event for a long time. Additionally, properly testing these parameters takes careful test procedures, so designs can slip through testing without showing signs of issues.
  • Finally, start-up or shutdown events are the next most likely cause for breaks. Sometimes there is overshoot during start-up, or the energy in the system is not properly dissipated during shutdown. A design can operate a long time without a start-up or shutdown, so they sometimes can slip through testing. Another fact about start-up and shutdown issues is that they can be dependent on multiple factors, such as input bulk capacitance, load, input voltage, and thermals. For example, if a ceramic or aluminum capacitor changes effective capacitance due to temperature, and a BJT current rating is also affected by temperature, then a particular case of load and input capacitance and BJT current could occur in deployment that was not observed in the lab.
• EMI Failure - there are two main tests for EMI: conducted emissions and radiated emissions. Conducted emissions are typically lower frequency (in EMI terms, around the switching frequency), and radiated emissions are higher frequency (example, 30 MHz).
  • Conducted emissions have a few fixes:
    • EMI choke
    • Increasing the common-mode capacitance
    • Decreasing the amount of copper a MOSFET has on a layout -- or shielding it with a ground plane
  • Radiated emissions have a few fixes:
    • Shielded cable
    • Shielded transformer
    • Ferrite beads *
    • Increasing the resistor on the gate of a MOSFET
    • Adjusting the snubber or RCD clamp on a MOSFET or switching diode – if the rise time period matches a frequency of concern, then that switching component is likely causing that EMI issue. Therefore, adjusting the clamp or snubber should help slow down the rise time which should help the EMI.
    • Metal casing of the entire design
    • Good ground planes with many vias connecting them across the layers
    • Putting ground planes next to critical switching traces
    • The overall PCB layout can contribute to EMI
    Note: * Make sure they are in series with the EMI choke; not in parallel.

• Common factors that lead to low efficiency:
  • Transformer selection: The transformer sets the foundation of the DC/DC since it has the primary inductance and turns ratios. Additionally, increased resistance here can lead to efficiency loss. Changing the size of the transformer can also affect the performance.
  • MOSFET or Diode selection:
    • Too slow
    • Too low of a Vds
    • Too small of a package
    • Too much charge or internal capacitance
    • Higher R_DS(ON)
    • Parts that have a wide tolerance for any/all of these parameters
  • Altering with resistors on snubbers or gate drives. These are tuned to the correct value, and changing them will result in more power being dissipated across them.
  • The switching frequency: changing the switching frequency will alter the DC/DC performance. First, the transformer primary inductance is specified for the specific switching frequency. The entire feedback network is also based on the switching frequency. The Current Sense output current threshold is based on the switching frequency. Additionally, the switching MOSFETs and diodes may not be fast enough for the new switching frequency. Their snubbers and RCD clamps will also need to be adjusted.
  • ACF Delay timing could be incorrect