SLVAF45 August 2021 TPS51397A , TPS566231 , TPS566235 , TPS566238 , TPS568230
2 Why We Need Cff in High Output Voltage D-CAP2/3 Converter for Stability
The bode plots of D-CAP2/D-CAP3 converters are shown as Figure 2-1. After the LC double poles frequency ω0 related with inductance and output capacitance, the slope of loop gain can be approximately seen as changing from 0 to -40dB/decade. With the zero injected by the internal ripple injection circuit, the slope becomes – 20dB/decade at 0dB, which could bring sufficient phase margin [7].
Figure 2-1 Bode Plot
of (a) D-CAP2 (b) D-CAP3 ConverterFor a stable D-CAP2/3 converter, if output voltage is increased with no other changes, the system will tend to become unstable, as shown in Figure 2-2. Since the gain before double poles frequency equals to Acp*Vref/Vo, system gain and crossover frequency ωcross will decrease with increasing Vo. If ωcross becomes lower than the frequency of ripple injection zero ωRI, system will have a -40dB/decade slope at 0dB, which may cause insufficient phase margin.
Figure 2-2 Loop Gain
of a D-CAP2 Converter (a) low Vo with
-20dB/Decade Crossing (b) high Vo with
-40dB/Decade CrossingFor some D-CAP2/3 converters similar to TPS548D22, the ripple injection zero frequency ωRI is adjustable with external configuration (sometimes named as ramp time constant, the ramp here is the ripple injection, time constant is the reciprocal of angular frequency). For TPS548D22, the Vref can also be adjusted for different output voltage to change ωcross. Those features can both help to adjust the relation of ωcross and ωRI and achieve -20dB/decade crossing.
But for most D-CAP2/3 devices to achieve easy design, the ripple injection zero frequency and reference voltage are fixed. So the LC double poles frequency ω0 must be increased for bandwidth improvement to ensure -20dB/decade slope at 0dB, as shown in Figure 2-3. However, it can be seen from Equation 1 that the inductance and output capacitance must be reduced to increase LC double poles frequency, which will cause large output ripple and noise. That causes the contradiction between output ripple and stability for D-CAP2/3 converters.
Figure 2-3 Loop Gain
of a D-CAP2 Converter (a) High Vo with
-40dB/Decade Crossing (b) Reducing L or
Co for -20dB/Decade CrossingIn application report https://www.ti.com/lit/pdf/SLVAF11, TPS568230 was used as an example to illustrate the stability design method for a 1.5 V Vo low output voltage application. Here the case with 5 V Vo is shown to reflect the contradiction between output ripple and stability in high output voltage application.
The condition for analysis is: Vin=12 V, Vo=5 V, Ioutmax=8 A, fsw=600kHz. First, the range of inductance can be got as 1.52uH-3.04uH, according to the principle to limit inductor current ripple as 20%-40% of Ioutmax.
Select inductor 744311220 L=2.2uH. Based on the previous proposed selection method of output capacitor, we could get the limits of Co as 4.7uF-22.3uF. With the upper limit Co=22.3uF, the output voltage ripple is too large to meet the requirement for lots of application.
It is obvious that reducing L or Co is just a trade-off solution between output voltage ripple and stability. Compared to that, adding feedforward capacitor Cff is a better solution to ensure converter stability.