SLVAEV7 September 2020 DRV8703-Q1
The failure mode distribution estimation for DRV8703-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| Low side gate turned ON, when commanded OFF | 20.5% |
| Low side gate turned OFF, when commanded ON | 16.0% |
| Low side gate to source voltage too high or too low | 0.5% |
| Low side gate driver slew rate too fast or too slow | 2.5% |
| High side gate turned ON, when commanded OFF | 20.5% |
| High side gate turned OFF, when commanded ON | 15.0% |
| High side gate to source voltage too high or too low | 0.5% |
| High side gate driver slew rate too fast or too slow | 3.5% |
| Dead time between high side FET and low side FET transition incorrect | 1.0% |
| Current sense feedback and regulation incorrect | 6.0% |
| Drain Source voltage monitoring incorrect | 4.0% |
| Incorrect communication or fault indication | 10.0% |
The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.