SLVAEU4A June 2020 – November 2025 TPS61175-Q1
The failure mode distribution estimation for TPS61175-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| SW no output | 35 |
| SW output not in specification voltage or timing | 50 |
| SW FET stuck on | 5 |
| EN fails or false enable | 5 |
| Short circuit any two pins | 5 |