SLVAEE5 June 2020 TPS23754
4.1 Maintain Power Signature (MPS)
According to IEEE802.3bt standard in Table 1, a valid Type-2 Maintain Power Signature (MPS) is a 10-mA pulse current for at least 75 ms every 310 ms. The NPN transistor 2N3904 plus divider resistor 200k and 15k act an important role to delay turn ON the new current source and to speed up the ramping time of Vout at beginning in order to meet the timing of MPS 310ms in the IEEE802.3bt standard. After 2N3904 turn ON, the new current source will be enabled to support the longer hiccup OCP OFF time at short circuit condition. The two ramping Vout slope can be observed at startup in Figure 10.
Table 1. PD DC Maintain Power Signature (MPS)
| Item | Parameter | Symbol | Units | Min | Max | Conditions |
|---|---|---|---|---|---|---|
| 1 | Total input current per the assigned Class, for single-signature PDs | |||||
| Class 1 to 4 | IPort_MPS | A | 0.01 | — | See 145.3.9 | |
| Class 5 to 8 | 0.016 | |||||
| 2 | Input current on each powered pairset for dual-signature PDs | |||||
| Class 1 to 5 | IPort_MPS-2P | A | 0.01 | — | — | |
| 3 | PD Maintain Power Signature Time | Tms | ms | 75 | — | long_class_event = FALSE |
| 7 | — | long_class_event = TRUE | ||||
| 4 | PD Drop Out Period | TMPDO_PD | ms | — | 250 | long_class_event = FALSE |
| — | 310 | long_class_event = TRUE | ||||
Figure 10. Startup Waveform with External Discrete Hiccup Circuit In the next generation PDs TPS2373x family, the ~25% hiccup duty ratio is integrated into TPS2373x. In the Figure 11, when overload or short circuit occur, VCC voltage goes low to hit its UVLO. Therefore, the startup source is turned back on and soft start cycle is reinitiated. SST is slowly discharged by 4 µA internal current source while PWM is stopped until reaching to a certain low level. There is new soft start cycle and the output voltage is ramped up. SST is charged with 10 µA.
Figure 11. TPS2373x Restart Following Severe Overload at Main Output of PSR Flyback DC-DC Converter