The BQ77307 device includes protections for cell voltage, pack current, and cell temperature, as well as integrated diagnostics. The timing for the evaluation of these protections is different for current versus the other protections. The cell voltages, internal and thermistor temperature, and the VREF and VSS diagnostics are evaluated at periodic intervals set by Power:Configuration:Voltage CHECK Time, which can be set from 250 ms to 255 seconds. The Short Circuit in Discharge (SCD) protection evaluates the differential voltage across the sense resistor (connected to the SRP and SRN pins) continuously, while the sense resistor voltage is evaluated every 305 μs to implement the Overcurrent in Charge (OCC) and Overcurrent in Discharge 1 and 2 (OCD1, OCD2) protections.

The BQ77307 device includes the capability to evaluate the internal die temperature versus selected thresholds using the difference between two internal transistor base-emitter voltages. This voltage difference is periodically compared to various thresholds, such as the Internal Overtemperature (OTINT) Protection based on Protections:Temperature:Internal Overtemperature Protection Threshold, and the internal overtemperature shutdown (based on Power:Shutdown:Shutdown Temperature).

The BQ77307 device also includes an evaluation of the voltage of an external thermistor on the TS pin to implement several temperature protections (OTC, OTD, UTC, UTD) described in later sections. The device uses an internal, factory trimmed 20-kΩ pullup resistor to bias an external thermistor during each evaluation. The TS pin is configured for thermistor evaluation using the Settings:Configuration:Eval Config[TSMODE] data memory setting. If the pin is not selected for thermistor evaluation, the pullup resistor is not enabled.

To provide a high precision result, the device uses the same 1.8-V internal LDO voltage for the detection threshold as is used for biasing the thermistor pullup resistor, thereby implementing a ratiometric evaluation that removes the error contribution from the LDO voltage level. Because the pullup resistor is only enabled during the periodic pin threshold evaluation, it is recommended to limit the capacitance at this node to less than 4 nF to reduce the effect of incomplete settling when the pullup resistor is biased.