SLLA565 September 2021 TUSB1044
When in the I2C mode, the TUSB1044 I2C address is defined by the UEQ0/A0 and UEQ1/A1 pin as shown in Table 3-1.
| Pin Combination | TUSB1044 I2C Address | ||
|---|---|---|---|
| UEQ1/A1 Pin2 Level | UEQ0/A0 Pin 35 Level | 7-bit I2C Address | Bit 0 (W/R) |
| 0 | 0 | 0x44 | 0/1 |
| 0 | R | 0x45 | 0/1 |
| 0 | F | 0x46 | 0/1 |
| 0 | 1 | 0x47 | 0/1 |
| R | 0 | 0x20 | 0/1 |
| R | R | 0x21 | 0/1 |
| R | F | 0x22 | 0/1 |
| R | 1 | 0x23 | 0/1 |
| F | 0 | 0x10 | 0/1 |
| F | R | 0x11 | 0/1 |
| F | F | 0x12 | 0/1 |
| F | 1 | 0x13 | 0/1 |
| 1 | 0 | 0x0C | 0/1 |
| 1 | R | 0x0D | 0/1 |
| 1 | F | 0x0E | 0/1 |
| 1 | 1 | 0x0F | 0/1 |
Table 3-2 lists the memory-mapped registers for the TUSB1044. Consider all register offset addresses not listed in Table 3-2 as reserved locations and do not modify the reserved register contents.
| Offset | Acronym | Register Name |
|---|---|---|
|
Ah |
General_1 |
General Register 1 |
|
Bh |
General_2 |
General Register 2 |
|
Ch |
General_3 |
General Register 3 |
|
10h |
UFP2_EQ |
UFP2 EQ Control |
|
11h |
UFP1_EQ |
UFP1 EQ Control |
|
12h |
DisplayPort_1 |
AUX Snoop Status |
|
13h |
DisplayPort_2 |
DP Lane Enable and Disable Control |
|
1Bh |
SOFT_RESET |
I2C and DPCS Soft Reset |
|
20h |
DFP2_EQ |
DFP2 EQ Control |
|
21h |
DFP1_EQ |
DFP1 EQ Control |
|
22h |
USB3_MISC |
Misc USB3 Controls |
|
23h |
USB3_LOS |
USB3 LOS Threshold Controls |