SLLA475 December 2020 TCAN1144-Q1 , TCAN1146-Q1
The TCAN1144-Q1 and TCAN1146-Q1 utilize interrupt registers for fault reporting. The global register is provided from the device whenever nCS is pulled low and valid clock provided on SCLK. This register provides information on where to find other interrupts.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GLOBALERR | RH | 0b | Logical OR of all interrupts |
| 6 | INT_1 | RH | 0b | Logical OR of INT_1 register |
| 5 | INT_2 | RH | 0b | Logical OR of INT_2 register |
| 4 | INT_3 | RH | 0b | Logical OR of INT_3 register |
| 3 | INT_CANBUS | RH | 0b | Logical OR of INT_CANBUS register |
| 2-0 | RSVD | R | 0000b | Reserved |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | WD | R/W1C | 0b | Watchdog event interrupt. NOTE: This interrupt bit will be set for every watchdog error event and does not reliy upon the Watchdog error counter |
| 6 | CANINT | R/W1C | 0b | CAN bus wake up interrupt |
| 5 | LWU | R/W1C | 0b | Local wake up |
| 4 | WKERR | R/W1C | 0b | Wake error bit is set when the SWE timer has expired and the state machine has returned to Sleep mode |
| 3 | FRAME_OVF | R/W1C | 0b | Frame error counter overflow |
| 2 | CANSLNT | R/W1C | 0b | CAN silent |
| 1 | CANTO | R/W1C | 0b | CAN timeout |
| 0 | CANDOM | R/W1C | 0b | CAN bus stuck dominant |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SMS | R/W1C | 0b | Sleep mode status flag. Only sets when sleep mode is entered by a WKERR, UVIO timeout or UVIO + TSD fault |
| 6 | PWRON | R/W1C | 1b | Power on |
| 5 | RSVD | R-0b | 0b | Reserved |
| 4 | UVSUP | R/W1C | 0b | VSUP undervoltage |
| 3 | UVIO | R/W1C | 0b | VIO undervoltage |
| 2 | UVCC | R/W1C | 0b | VCC undervoltage |
| 1 | TSD | R/W1C | 0b | Thermal Shutdown |
| 0 | TSDW | R/W1C | 0b | Thermal Shutdown Warning |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SPIERR | R/W1C | 0b | Sets when SPI status bit sets |
| 6 | SWERR | RH | 0b | Logical OR of (SW_EN=1 and NOT(SWCFG)) and FRAME_OVF. Selective Wake may not be enabled while SWERR is set |
| 5 | FSM | R/W1C | 0b | Entered fail-safe mode. Can be cleared while in fail-safe mode. |
| 4-1 | RSVD | R | 0000b | Reserved |
| 0 | CRC_EEPROM | R/W1C | 0b | EEPROM CRC error |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RSVD | R | 0b | Reserved |
| 6 | CANBUSTERMOPEN | R/W1C | 0b | CAN bus has one termination point open |
| 5 | CANHCANL | R/W1C | 0b | CANH and CANL shorted together |
| 4 | CANHBAT | R/W1C | 0b | CANH shorted to Vbat |
| 3 | CANLGND | R/W1C | 0b | CANL shorted to GND |
| 2 | CANBUSOPEN | R/W1C | 0b | CAN bus open |
| 1 | CANBUSGND | R/W1C | 0b | CAN bus shorted to GND or CANH shorted to GND |
| 0 | CANBUSBAT | R/W1C | 0b | CAN bus shorted to Vbat or CANL shorted to Vbat |