SLAZ279AA October 2012 – May 2021 MSP430F5418
SYS Module
Functional
Timing of USCI interrupts may cause PC corruption due to automatic clear of an IFG
When certain USCI I2C interrupt flags (IFG) are set and an automatic flag-clearing event on the I2C bus occurs, the address bus will default to FFFEh (Reset Vector) and the data bus to the opcode for the RETI instruction. This means the program counter defaults to FFFEh (Reset Vector) during this period of time. This will only happen when the IFG is cleared within a critical time window (~6 CPU clock cycles) after a USCI interrupt request occurs and before the interrupt servicing is initiated. The affected interrupts are UCBxTXIFG, UCSTPIFG, UCSTTIFG and UCNACKIFG.
The automatic flag-clearing scenarios are described in the following situations:
- A pending UCBxTXIFG interrupt request is cleared on the falling SCL clock edge following a NACK.
- A pending UCSTPIFG, UCSTTIFG, or UCNACKIFG interrupt request is cleared by a following Start condition.
If an NMI request occurs during the time that the PC holds the default value FFFEh before the default RETI instruction is executed, the PC will be corrupted on return from the NMI ISR. This is because the previous PC contents of FFFEh were stored onto the stack as the address of the next instruction to be executed. The CPU consequently interprets the address in FFFEh as an instruction (errant behavior) and because the default RETI was never executed, the stack pointer remains decreased by four (errant behavior).
Prevent the flag-clearing event from interrupting the servicing of the affected USCI IFG's.
- Poll the affected USCI flags instead of enabling the interrupts.
or
- Ensure the above mentioned flag-clearing events occur after a time delay of 6 CPU clock cycles after the interrupt requests occur and are accepted.