Figure 4-1 and Figure 4-2 show the TLV709 pin diagrams for the PK (3-Pin
SOT-89) package. For a detailed description of the device
pins, see the Pin Configuration and Functions section in the TLV709 data sheet.
Figure 4-3 Pin Diagram (PK (3-Pin SOT-89), IN Tab Package)Figure 4-4 Pin Diagram (PK (3-Pin SOT-89), GND
Tab Package)
Table 4-6 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name
Pin No.
Description of Potential Failure Effects
Failure Effect Class
OUT
3
Regulation is not possible, the device operates at
current limit. The device can cycle in and out of thermal shutdown.
B
1
IN
2
Power is not supplied to the device. System
performance depends on upstream current limiting.
B
3
GND
1
No effect. Normal operation.
D
2
Table 4-7 Pin FMA for Device Pins Open-Circuited
Pin Name
Pin No.
Description of Potential Failure Effects
Failure Effect Class
OUT
3
The device output is disconnected from the
load.
B
1
IN
2
Power is not supplied to the device.
B
3
GND
1
Ground loop parasitics are increased and transient
performance can be degraded.
C
2
Table 4-8 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name
Pin No.
Shorted to
Description of Potential Failure Effects
Failure Effect Class
OUT
3
IN
Regulation is not possible. VOUT = VIN.
B
1
IN
2
GND
Power is not supplied to the device.
B
3
GND
1
OUT
Regulation is not possible; the device operates at
current limit. The device can cycle in and out of thermal shutdown.
B
2
Table 4-9 Pin FMA for Device Pins Short-Circuited to Supply
Pin Name
Pin No.
Description of Potential Failure Effects
Failure Effect Class
OUT
3
Regulation is not possible. VOUT =
VIN .
B
1
IN
2
No effect. Normal operation.
D
3
GND
1
Power is not supplied to the device. System
performance depends on upstream current limiting.
B
2