SFFSAA4 July 2025 TPS62893-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the TPS6289xx-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to VIN (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the TPS6289xx-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPS6289xx-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Assumes the device is running in the typical application, please refer to the Simplified Schematics in the TPS6287x-Q12.7V to 6V Input, 6-A/9-A/12-A/15-A, Automotive, Stackable, Synchronous Step-Down Converters With Fast Transient Response data sheet.
Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| MODE/SYNC | 1 | Power-save mode is enabled. Normal operation. | C |
| EN | 2 | The device is disabled. Normal operation. | B |
| VIN | 3 | The device does not power up and there is no output voltage. | B |
| GND | 4 | Normal operation. | D |
| SW | 5 | Potential device damage. | A |
| GND | 6 | Normal operation. | D |
| VIN | 7 | The device does not power up and there is no output voltage. | B |
| SYNC_OUT | 8 | No regulated output voltage. | B |
| PG | 9 | Normal operation and loss of PG indication. | B |
| SDA | 10 | Normal operation and no I2C communication. | B |
| SCL | 11 | Normal operation and no I2C communication. | B |
| SET4 | 12 | Normal operation. Defines I2C address. | B |
| SET3 | 13 | Normal operation. Defines output voltage range and mode of operation. | B |
| SET2 | 14 | Normal operation. Defines start-up voltage, phase shift, and I2 address. | B |
| VOSNS | 15 | Maximum duty cycle operation and no regulated output voltage. Output voltage follows the input voltage. | B |
| GOSNS | 16 | Normal operation, but output voltage accuracy declines. | C |
| COMP | 17 | The device does not power up and there is no output voltage. | B |
| AGND | 18 | Normal operation. | D |
| SET1 | 19 | Normal operation. Defines start-up voltage, phase shift, and I2 address. | D |
| GND | 20 | Normal operation. | D |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| MODE/SYNC | 1 | Power-save mode is enabled. Normal operation. | C |
| EN | 2 | The device is disabled. Normal operation. | B |
| VIN | 3 | Normal operation. Pin 7 is still connected. | C |
| GND | 4 | Normal operation. Pin 6 and Pin 20 are still connected. | C |
| SW | 5 | No output voltage. | B |
| GND | 6 | Normal operation. Pin 4 and Pin 20 are still connected. | C |
| VIN | 7 | Normal operation. Pin 3 is still connected. | C |
| SYNC_OUT | 8 | Normal operation. | D |
| PG | 9 | Normal operation and loss of PG indication. | B |
| SDA | 10 | Normal operation and no I2C communication. | B |
| SCL | 11 | Normal operation and no I2C communication. | B |
| SET4 | 12 | Normal operation. I2C address is undefined. | B |
| SET3 | 13 | Normal operation. Output voltage range and mode of operation are undefined. | B |
| SET2 | 14 | Normal operation. Start-up voltage, phase shift, and I2 address are undefined. | B |
| VOSNS | 15 | No output voltage regulation, which can cause the output voltage to oscillate. Oscillation frequency cannot be predicted. | B |
| GOSNS | 16 | No output voltage regulation, which can cause the output voltage to oscillate. Oscillation frequency cannot be predicted. | B |
| COMP | 17 | No loop compensation, which can cause the output voltage to oscillate. Oscillation frequency cannot be predicted. | B |
| AGND | 18 | Normal operation. Pin 4, Pin 6, and Pin 20 are still connected. | C |
| SET1 | 19 | Normal operation. Start-up voltage, phase shift, and I2 address are undefined. | B |
| GND | 20 | Normal operation. Pin 4 and Pin 6 are still connected. | C |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| MODE/SYNC | 1 | 2 | Forced PWM operation if EN is high. Device disabled otherwise. | C |
| EN | 2 | 3 | Potential device damage. | A |
| VIN | 3 | 4 | The device does not power up and there is no output voltage. | B |
| GND | 4 | 5 | Potential device damage. | A |
| SW | 5 | 6 | Potential device damage. | A |
| GND | 6 | 7 | The device does not power up and there is no output voltage. | B |
| VIN | 7 | 8 | No output voltage. | B |
| SYNC_OUT | 8 | 9 | Potential device damage. | A |
| PG | 9 | 10 | Normal operation, loss of PG indication, and no I2C communication. | B |
| SDA | 10 | 11 | Normal operation and no I2C communication. | B |
| SCL | 11 | 12 | Normal operation. I2C address is undefined. | B |
| SET4 | 12 | 13 | Normal operation. I2C address, output voltage range, and mode of operation is undefined. | B |
| SET3 | 13 | 14 | Normal operation. Output voltage range, mode of operation and start-up voltage, phase shift, and I2 address is undefined. | B |
| SET2 | 14 | 15 | Output voltage regulation is undefined, maximum duty cycle operation, and no regulated output voltage. Output voltage follows the input voltage, or no output voltage. | B |
| VOSNS | 15 | 16 | Maximum duty cycle operation and no regulated output voltage. Output voltage follows the input voltage. | B |
| GOSNS | 16 | 17 | The device does not power up and there is no output voltage. | B |
| COMP | 17 | 18 | The device does not power up and there is no output voltage. | B |
| AGND | 18 | 19 | Normal operation. Defines start-up voltage, phase shift, and I2 address. | B |
| SET1 | 19 | 20 | Normal operation. Defines start-up voltage, phase shift, and I2 address. | B |
| GND | 20 | 1 | Normal operation. Power-save mode is enabled. | B |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to VIN
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| MODE/SYNC | 1 | Forced PWM operation. Normal operation. | C |
| EN | 2 | Potential device damage. | A |
| VIN | 3 | Normal operation. | D |
| GND | 4 | The device does not power up and there is no output voltage. | B |
| SW | 5 | Potential device damage. | A |
| GND | 6 | The device does not power up and there is no output voltage. | B |
| VIN | 7 | Normal operation. | D |
| SYNC_OUT | 8 | Potential device damage. | A |
| PG | 9 | Potential device damage. | A |
| SDA | 10 | Potential device damage. | A |
| SCL | 11 | Potential device damage. | A |
| SET4 | 12 | Normal operation. Defines I2C address. | B |
| SET3 | 13 | Normal operation. Defines output voltage range and mode of operation. | B |
| SET2 | 14 | Normal operation. Defines start-up voltage, phase shift, and I2 address. | B |
| VOSNS | 15 | The device does not start up. Output voltage stays low. | B |
| GOSNS | 16 | Potential device damage. | A |
| COMP | 17 | Potential device damage. | A |
| AGND | 18 | The device does not power up and there is no output voltage. Potential device damage. | B |
| SET1 | 19 | Normal operation. Defines start-up voltage, phase shift, and I2 address. | B |
| GND | 20 | The device does not power up and there is no output voltage. | B |