SFFSA04 October 2024 LM704A0-Q1
5 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the LM704A0-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 5-2)
- Pin open-circuited (see Table 5-3)
- Pin short-circuited to an adjacent pin (see Table 5-4)
- Pin short-circuited to VIN (see Table 5-5)
Table 5-2 through Table 5-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 5-1.
Table 5-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 5-1 shows the LM704A0-Q1 pin diagram. For a detailed description of the device pins, refer to the Pin Configuration and Functions section in the LM704A0-Q1 data sheet.
Figure 5-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Application Circuit is used per the LM704A0-Q1 data
sheet
- PG is pulled up to VDDA
Table 5-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN | 1-3 | VOUT = 0V | B |
| CBOOT | 4 | VOUT = 0V, VCC regulator loaded to Current Limit | B |
| SW | 5 | VOUT = 0V, high-side FET shorted from VIN to GND | A |
| BIAS | 6 | VOUT = expected VOUT, internal VCC regulator provides bias voltage | D |
| PGOOD | 7 | VOUT = expected VOUT | D |
| PFM/SYNC | 8 | VOUT = expected VOUT, no synchronization possible and is in FPWM mode | C |
| EN/UVLO | 9 | VOUT = 0V, enters shutdown mode | B |
| NC | 10 | N/A | D |
| ISNS+ | 11 | VOUT = 0V, HO damaged | A |
| VOUT | 12 | Current limit reached, VOUT = 0V and enters hiccup mode | B |
| CONFIG | 13 | Expected VOUT, spread spectrum and multiphase mode disabled | C |
| RT | 14 | VOUT = expected VOUT, FSW at maximum causing maximum power dissipation | C |
| EXTCOMP | 15 | VOUT = 0V | B |
| FB | 16 | Internal FB MODE, VOUT = expected VOUT | D |
| External FB MODE VOUT = VIN | A | ||
| AGND | 17 | AGND is GND, VOUT = expected VOUT | D |
| VDDA | 18 | VOUT = 0V, no switching, loaded VCC output | B |
| VCC | 19 | VOUT = 0V, no switching, loaded VCC output | B |
| SW | 20-22 | VOUT = 0V, high-side FET shorted from VIN to GND | A |
| PGND | 23-26 | PGND is GND, VOUT = expected VOUT | D |
| VIN | 27-29 | VOUT = 0V | B |
Table 5-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN | 1-3 | VOUT = expected VOUT, part works through VIN on pins 27-29 | D |
| CBOOT | 4 | VOUT = 0V | B |
| SW | 5 | VOUT = expected VOUT, part works through SW on pins 20-22 | D |
| BIAS | 6 | VCC working off internal VCC regulator | D |
| PGOOD | 7 | If in single mode, PGOOD has no effect on operation | D |
| If in multiphase primary mode, the secondary detects no clock input and shuts down | B | ||
| PFM/SYNC | 8 | VOUT = expected VOUT | C |
| EN/UVLO | 9 | Device state in indeterminate | B |
| NC | 10 | VOUT = expected VOUT | D |
| ISNS+ | 11 | OPEN current sense pin blocks current limit and causes VOUT oscillations | A |
| VOUT | 12 | VOUT = 0V | B |
| CONFIG | 13 | CONFIG is used during start up, VOUT = expected VOUT | D |
| RT | 14 | RT regulates to 500mV but internal oscillator does not function | B |
| EXTCOMP | 15 | VOUT oscillates, if VOUT oscillates to VIN, damage can occur if VIN > 60V | A |
| FB | 16 | If external FB mode, VOUT is indeterminate | B |
| If Internal FB mode, VOUT operates normally | D | ||
| AGND | 17 | VOUT is indeterminate | D |
| VDDA | 18 | Poor noise immunity | D |
| VCC | 19 | VOUT = expected VOUT until damage occurs | A |
| SW | 20-22 | VOUT = 0V | B |
| PGND | 23-26 | VOUT is indeterminate | B |
| VIN | 27-29 | VOUT = expected VOUT, part works through VIN on pins 1-3 | D |
Table 5-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| NC | 1 | NC | No impact | D |
| NC | 2 | CNFG | No impact | D |
| CNFG | 3 | RT | VOUT = expected VOUT with erratic switching | B |
| RT | 4 | EXTCOMP | COMP cannot regulate down due to clamping by internal RT | B |
| EXTCOMP | 5 | FB | External FB mode: COMP regulates to 0.8V and output is
unregulated, VOUT = indeterminate | B |
| Internal FB mode: COMP rises up to VDDA, VOUT = VIN | A | |||
| FB | 6 | AGND | External FB mode: VOUT = VIN | A |
| Internal FB mode: VOUT = expected VOUT | D | |||
| AGND | 7 | VDDA | VDDA is grounded, VOUT = 0V | B |
| VDDA | 8 | VCC | VOUT = expected VOUT | D |
| VCC | 9 | PGND | VCC is grounded, VOUT = 0V | B |
| PGND | 10 | LO | VOUT = 0V, VCC is loaded by the LO driver | B |
| LO | 11 | VIN | VOUT = 0V, the driver is damaged if VIN > 6.5V | A |
| VIN | 12 | HO | VOUT = VIN | A |
| HO | 13 | SW | VOUT = 0V | B |
| SW | 14 | CBOOT | VOUT = 0V | B |
| CBOOT | 15 | VCCX | VOUT < 5V | A |
| VCCX | 16 | PG | PG pulldown can damage, VOUT = expected VOUT | A |
| PG | 17 | PFM/SYNC | VOUT = expected VOUT | C |
| PFM/SYNC | 18 | EN | VOUT = expected VOUT | A |
| EN | 19 | ISNS+ |
EN is high-voltage rated, VOUT = expected VOUT, if VOUT > 1V If VOUT < 1V, the device is disabled | B |
| ISNS+ | 20 | VOUT |
Current limit is disabled since the current limit resistor is shorted VOUT cannot regulate since current mode feedback is shorted | A |
| VOUT | 21 | NC | No impact | D |
| NC | 22 | NC | No impact | D |
| NC | 23 | NC | No impact | D |
| NC | 24 | NC | No impact | D |
Table 5-5 Pin FMA for Device Pins
Short-Circuited to
VIN
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN | 1-3 | No impact | D |
| CBOOT | 4 | If VIN < 6.5V, VOUT = expected VOUT, erratic switching | C |
| If VIN > 6.5V, exceeds max ratings and CBOOT pin is damaged, HO bias damage | A | ||
| SW | 5 | VOUT=VIN, excess current from VIN through low-side FET | B |
| BIAS | 6 | If VIN < 40V, VOUT = expected VOUT | D |
| If VIN > 40V, exceeds maximum ratings and the pin VCC is damaged, VOUT = 0V | A | ||
| PGOOD | 7 | If VIN < 6.5V, VOUT = expected, PG possibly forced high exceeding the PG pulldown SOA | B |
| If VIN > 6.5V, exceeds maximum ratings and pin PG is destroyed, VOUT = expected VOUT | B | ||
| PFM/SYNC | 8 | If VIN < 6.5V, VOUT = expected VOUT | D |
| If VIN > 6.5V, exceeds maximum ratings and pin
PFM/SYNC is destroyed VOUT = expected VOUT |
D | ||
| EN/UVLO | 9 | Part is always be enabled, VOUT = expected VOUT | C |
| NC | 10 | No impact | D |
| ISNS+ | 11 | if VIN < 6.5V, VOUT = VIN | B |
| If VIN > 60V, exceeds maximum ratings and pin ISNS+ is damaged. VOUT = VIN | A | ||
| VOUT | 12 | If VIN < 6.5V, VOUT = VIN | D |
| If VIN > 60V, exceeds maximum ratings and pin VOUT is damaged, VOUT = VIN | A | ||
| CONFIG | 13 | If VIN < 6.5V, VOUT = expected VOUT | B |
| If VIN > 6.5V, exceeds maximum ratings and pin CONFIG is destroyed | A | ||
| RT | 14 | If VIN < 6.5V, VOUT= 0V as frequency goes to 0Hz | B |
| If VIN > 6.5V, exceeds maximum ratings and pin RT is destroyed | A | ||
| EXTCOMP | 15 | This brings VCC up to VIN, VOUT = VIN | A |
| FB | 16 | If VIN > 16V (fixed version) or 5.5V (adjustable version) damage occurs,VOUT = 0V | B |
| AGND | 17 | VIN shorts to GND, VOUT = 0V | A |
| VDDA | 18 | If VIN < 6.5V, no impact | D |
| If VIN > 6.5V, exceeds maximum ratings and pin VDDA is damaged | A | ||
| VCC | 19 | If VIN < 12V, no impact | D |
| If VIN > 12V, exceeds maximum ratings and pin VCC is damaged | A | ||
| SW | 20-22 | VOUT = VIN, excess current from VIN through low-side FET | B |
| PGND | 23-26 | VIN shorts to GND. VOUT = 0V | A |
| VIN | 27-29 | No impact | D |