SFFS194 September 2021 LM25148-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the LM25148-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the LM25148-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM25148-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Application Circuit as per the LM25148(-Q1)
datasheet is used
- PG is pulled-up to VOUT
Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| NC | 1 | NC can be connected to Ground for improved heat spreading. | D |
| NC | 2 | NC can be connected to Ground for improved heat spreading. | D |
| CNFG | 3 | VOUT is unaffected. | C |
| RT | 4 | VOUT will attempt to regulate at maximum fSW, causing maximum power disippation. | B |
| EXTCOMP | 5 | VOUT = 0 V | B |
| FB | 6 | Internal FB mode, VOUT = expected VOUT | D |
| External FB mode, VOUT = VIN | A | ||
| AGND | 7 | AGND is GND. VOUT = expected VOUT | D |
| VDDA | 8 | VOUT = 0 V, no switching, loaded VCC output | B |
| VCC | 9 | VOUT = 0 V, no switching, loaded VCC output | B |
| PGND | 10 | PGND is GND. VOUT = expected VOUT | D |
| LO | 11 | VOUT = 0 V, the VCC regulator loaded to current limit. | B |
| VIN | 12 | VOUT = 0 V | B |
| HO | 13 | VOUT = 0 V, the VCC regulator loaded to current limit. | B |
| SW | 14 | VOUT = 0 V. High-side FET is shorted from VIN to GND. | A |
| CBOOT | 15 | VOUT = 0 V, the VCC regulator loaded to current limit. | B |
| VCCX | 16 | VOUT = expected VOUT. Internal VCC regulator provides bias voltage. | C |
| PG | 17 | If in single phase, PG has no effect on operation. VOUT = expected VOUT | C |
| If in interleaved primary mode, the secondary will detect no clock input and will shut down. Secondary phase is disabled and primary phase can current limit. | B | ||
| PFM/SYNC | 18 | VOUT = expected VOUT. No synchronization will be available and LM25148/LM25148-Q1 will be in FPWM mode. | C |
| EN | 19 | VOUT = 0 V, the LM25148-Q1 enters shutdown. | C |
| ISNS+ | 20 | VOUT = 0 V, HO damaged | A |
| VOUT | 21 | VOUT = 0 V. Current limit reached, hiccup mode occurs. | B |
| NC | 22 | NC can be connected to Ground for improved heat spreading. | D |
| NC | 23 | NC can be connected to Ground for improved heat spreading. | D |
| NC | 24 | NC can be connected to Ground for improved heat spreading. | D |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| NC | 1 | NC can be open-circuited. | D |
| NC | 2 | NC can be open-circuited. | D |
| CNFG | 3 | VOUT will continue operating normally. CNFG is used during start-up. | C |
| RT | 4 | RT will regulate to 500 mV, but the internal oscillator will not function. | B |
| EXTCOMP | 5 | VOUT will oscillate. If VOUT oscillates to VIN, damage can occur if VIN > 36 V. | A |
| FB | 6 | Internal FB mode, VOUT = expected VOUT | D |
| External FB mode, VOUT = VIN | A | ||
| AGND | 7 | VOUT is indeterminate. | B |
| VDDA | 8 | Poor noise immunity | C |
| VCC | 9 | VOUT = 0 V | B |
| PGND | 10 | VOUT = 0 V | B |
| LO | 11 | VOUT = expected VOUT with reduced efficiency. | C |
| VIN | 12 | VOUT = 0 V | C |
| HO | 13 | If HO is opened while HO to SW has voltage, the high-side FET will never turn off. VOUT = VIN | A |
| SW | 14 | VOUT is indeterminate. The CBOOT floating rail has no reference to the actual SW node. VOUT = VIN | A |
| CBOOT | 15 | VOUT = 0 V | B |
| VCCX | 16 | VCCX held to ground by weak pulldown, VOUT = expected VOUT | D |
| PG | 17 | If in single phase, PG has no effect on operation. VOUT = expected VOUT | C |
| If in interleaved primary mode, the secondary will detect no clock input and will shut down. Secondary phase is disabled and primary phase can current limit. | B | ||
| PFM/SYNC | 18 | VOUT = expected VOUT | D |
| EN | 19 | VOUT = expected VOUT | D |
| ISNS+ | 20 | The OPEN ISNS+ pin will block current limit and cause VOUT oscillations. | A |
| VOUT | 21 | VOUT = 0 V | B |
| NC | 22 | NC can be open-circuited. | D |
| NC | 23 | NC can be open-circuited. | D |
| NC | 24 | NC can be open-circuited. | D |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| NC | 1 | NC | No impact | D |
| NC | 2 | CNFG | No impact | D |
| CNFG | 3 | RT | VOUT = expected VOUT with erractic switching | B |
| RT | 4 | EXTCOMP | COMP cannot regulate down due to clamping by internal RT. | B |
| EXTCOMP | 5 | FB | External FB mode: COMP will regulate to 0.8 V and output will be unregulated. VOUT = indeterminate | B |
| Internal FB mode: COMP will rise up to VDDA. VOUT = VIN | A | |||
| FB | 6 | AGND | External FB mode: VOUT = VIN | A |
| Internal FB mode: VOUT = expected VOUT | D | |||
| AGND | 7 | VDDA | VDDA will be grounded. VOUT = 0 V | B |
| VDDA | 8 | VCC | VOUT = expected VOUT | D |
| VCC | 9 | PGND | VCC will be grounded. VOUT = 0 V | B |
| PGND | 10 | LO | VOUT = 0 V. VCC is loaded by the LO driver. | B |
| LO | 11 | VIN | VOUT = 0 V. The driver will be damaged if VIN > 6.5 V. | A |
| VIN | 12 | HO | VOUT = VIN | A |
| HO | 13 | SW | VOUT = 0 V | B |
| SW | 14 | CBOOT | VOUT = 0 V | B |
| CBOOT | 15 | VCCX | VOUT < 5 V | A |
| VCCX | 16 | PG | PG pulldown can damage, VOUT = expected VOUT | A |
| PG | 17 | PFM/SYNC | VOUT = expected VOUT | C |
| PFM/SYNC | 18 | EN | VOUT = expected VOUT | A |
| EN | 19 | ISNS+ | EN is high-voltage rated. VOUT = expected VOUT if VOUT > 1 V. If VOUT < 1 V, the device is disabled. | B |
| ISNS+ | 20 | VOUT | Current limit is disabled since the current limit resistor would be shorted. VOUT cannot regulate since current mode feedback is shorted. | A |
| VOUT | 21 | NC | No impact | D |
| NC | 22 | NC | No impact | D |
| NC | 23 | NC | No impact | D |
| NC | 24 | NC | No impact | D |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to
VIN
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| NC | 1 | No impact | D |
| NC | 2 | No impact | D |
| CNFG | 3 | VOUT = VIN | A |
| RT | 4 | VOUT = 0 V, high VIN current | A |
| EXTCOMP | 5 | This will bring VDDA up to VIN. VOUT = VIN | A |
| FB | 6 | This will bring VDDA up to VIN. VOUT = VIN | A |
| AGND | 7 | VOUT = VIN, high VIN current | A |
| VDDA | 8 | If VIN < 6.5 V, VOUT = expected VOUT | D |
| If VIN > 6.5 V, exceeds maximum ratings and VDDA is damaged. | A | ||
| VCC | 9 | If VIN < 6.5 V, VOUT = expected VOUT | D |
| If VIN > 6.5 V, exceeds maximum ratings and VCC is damaged. | A | ||
| PGND | 10 | VOUT = VIN, high VIN current | A |
| LO | 11 | For VIN < 6.5 V, VOUT = 0; excess current from VIN | B |
| For VIN > 6.5 V, exceeds maximum ratings and the LO pin is damaged. | A | ||
| VIN | 12 | N/A | D |
| HO | 13 | For VIN < 6.5 V, VOUT = dropout lower than VIN, no switching, and excess current from VIN | B |
| For VIN > 6.5 V, exceeds maximum ratings and the HO pin is damaged, VOUT = VIN | A | ||
| SW | 14 | VOUT = VIN, excess current from VIN. LO turns on and shorts against VIN. | A |
| CBOOT | 15 | For VIN < 6.5 V, VOUT = expected VOUT, erratic switching | B |
| For VIN > 6.5 V, exceeds maximum ratings and the CBOOT pin is damaged, HO damaged. VOUT = VIN | A | ||
| VCCX | 16 | If VCCX = VOUT, for VIN < 6.5 V, VOUT = VIN | B |
| For VIN > 6.5 V, exceeds maximum ratings and the VCCX pin is damaged. | A | ||
| PG | 17 | For VIN < 6.5 V, VOUT = regulated and PG forced high | B |
| For VIN > 6.5 V, exceeds maximum ratings and PG is destroyed. | A | ||
| PFM/SYNC | 18 | If PFM = GND, VOUT=0 V, excess current from VIN | B |
| If PFM = VDDA and VIN < 6.5 V, VOUT = expected VOUT. Erratic switching | B | ||
| If VIN > 6.5 V, exceeds maximum ratings and the PFM/SYNC pin is damaged, VOUT = expected VOUT | A | ||
| EN | 19 | The LM25148-Q1 will be always on. VOUT = expected VOUT | C |
| ISNS+ | 20 | If VIN < 36 V, VOUT = VIN | B |
| If VIN > 36 V, exceeds maximum ratings and the CS pin is damaged. | A | ||
| VOUT | 21 | If VIN < 36 V, VOUT = VIN | B |
| If VIN > 36 V, exceeds maximum ratings and the CS pin is damaged. | A | ||
| NC | 22 | No impact | D |
| NC | 23 | No impact | D |
| NC | 24 | No impact | D |