激情五月开心综合亚洲 ,美女裸体自慰在线观看,亚洲国产成人一区二区在线

ZHCSCU6A June 2014 – September 2014 ULN2003B

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

N|16
- MPDI002C
PW|16
- MPDS361B
D|16
- MPDS178G

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcscu6a_oa

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

at 25°C free-air temperature (unless otherwise noted)

			MIN	MAX	UNIT
V_CC	Collector-emitter voltage			50	V
	Clamp diode reverse voltage⁽²⁾			50	V
V_I	Input voltage⁽²⁾			30	V
	Peak collector current⁽³⁾⁽⁴⁾			500	mA
I_OK	Output clamp current			500	mA
	Total emitter-terminal current			–2.5	A
T_A	Operating free-air temperature range		–40	105	°C
θ_JA	Package thermal impedance⁽³⁾⁽⁴⁾	D package		81	°C/W
		N package		49.7
		PW package		105
T_J	Operating virtual junction temperature			150	°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.

(3) Maximum power dissipation is a function of T_J(max), θ_JA, and T_A. The maximum allowable power dissipation at any allowable ambient temperature is P_D = (T_J(max) – T_A)/θ_JA. Operating at the absolute maximum T_J of 150°C can affect reliability.

(4) The package thermal impedance is calculated in accordance with JESD 51-7.

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾		500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_I		0	5	V
V_CC		0	50	V
T_J	Junction Temperature	-40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ULN2003B		UNIT
		PW	D
		16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	105.4	81.2	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	32.9	40.3
R_θJB	Junction-to-board thermal resistance	51.3	38.9
ψ_JT	Junction-to-top characterization parameter	2.1	10.9
ψ_JB	Junction-to-board characterization parameter	50.6	38.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics, T_A = 25°C

PARAMETER		TEST FIGURE	TEST CONDITIONS		ULN2003B			UNIT
PARAMETER		TEST FIGURE	TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_I(on)	On-state input voltage	Figure 12	V_CE = 2 V	I_C = 200 mA			2.4	V
				I_C = 250 mA			2.7
				I_C = 300 mA			3
V_CE(sat)	Collector-emitter saturation voltage	Figure 11	I_I = 250 μA,	I_C = 100 mA		0.9	1.1	V
			I_I = 350 μA,	I_C = 200 mA		1	1.3
			I_I = 500 μA,	I_C = 350 mA		1.2	1.6
I_CEX	Collector cutoff current	Figure 8	V_CE = 50 V,	I_I = 0			10	μA
V_F	Clamp forward voltage	Figure 14	I_F = 350 mA			1.7	2	V
I_I(off)	Off-state input current	Figure 9	V_CE = 50 V,	I_C = 500 μA	50	65		μA
I_I	Input current	Figure 10	V_I = 3.85 V			0.93	1.35	mA
I_R	Clamp reverse current	Figure 13	V_R = 50 V				50	μA
C_i	Input capacitance		V_I = 0,	f = 1 MHz		15	25	pF

7.6 Electrical Characteristics, T_A = –40°C to 105°C

PARAMETER		TEST FIGURE	TEST CONDITIONS		ULN2003B			UNIT
PARAMETER		TEST FIGURE	TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_I(on)	On-state input voltage	Figure 12	V_CE = 2 V	I_C = 200 mA			2.7	V
				I_C = 250 mA			2.9
				I_C = 300 mA			3
V_CE(sat)	Collector-emitter saturation voltage	Figure 11	I_I = 250 μA,	I_C = 100 mA		0.9	1.2	V
			I_I = 350 μA,	I_C = 200 mA		1	1.4
			I_I = 500 μA,	I_C = 350 mA		1.2	1.7
I_CEX	Collector cutoff current	Figure 8	V_CE = 50 V,	I_I = 0			20	μA
V_F	Clamp forward voltage	Figure 14	I_F = 350 mA			1.7	2.2	V
I_I(off)	Off-state input current	Figure 9	V_CE = 50 V,	I_C = 500 μA	30	65		μA
I_I	Input current	Figure 10	V_I = 3.85 V			0.93	1.35	mA
I_R	Clamp reverse current	Figure 13	V_R = 50 V				100	μA
C_i	Input capacitance		V_I = 0,	f = 1 MHz		15	25	pF

7.7 Switching Characteristics, T_A = 25°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_PLH	Propagation delay time, low- to high-level output				0.25	1	μs
t_PHL	Propagation delay time, high- to low-level output				0.25	1	μs
V_OH	High-level output voltage after switching	V_S = 50 V,	I_O ≈ 300 mA	V_S – 20			mV

7.8 Switching Characteristics, T_A = –40°C to 105°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_PLH	Propagation delay time, low- to high-level output				1	10	μs
t_PHL	Propagation delay time, high- to low-level output				1	10	μs
V_OH	High-level output voltage after switching	V_S = 50 V,	I_O ≈ 300 mA	V_S – 50			mV