ZHCSDF1 February 2015 UCD90240
PRODUCTION DATA.

| PIN | I/O TYPE |
DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ANALOG MONITOR PINS | |||
| MON1 | E2 | I | Analog input monitor pin |
| MON2 | E1 | I | Analog input monitor pin |
| MON3 | F2 | I | Analog input monitor pin |
| MON4 | F1 | I | Analog input monitor pin |
| MON5 | B3 | I | Analog input monitor pin |
| MON6 | A3 | I | Analog input monitor pin |
| MON7 | B4 | I | Analog input monitor pin |
| MON8 | A4 | I | Analog input monitor pin |
| MON9 | B5 | I | Analog input monitor pin |
| MON10 | A5 | I | Analog input monitor pin |
| MON11 | B6 | I | Analog input monitor pin |
| MON12 | A6 | I | Analog input monitor pin |
| MON13 | C1 | I | Analog input monitor pin |
| MON14 | C2 | I | Analog input monitor pin |
| MON15 | B1 | I | Analog input monitor pin |
| MON16 | B2 | I | Analog input monitor pin |
| MON17 | G2 | I | Analog input monitor pin |
| MON18 | G1 | I | Analog input monitor pin |
| MON19 | H1 | I | Analog input monitor pin |
| MON20 | H2 | I | Analog input monitor pin |
| MON21 | B7 | I | Analog input monitor pin |
| MON22 | A7 | I | Analog input monitor pin |
| MON23 | B8 | I | Analog input monitor pin |
| MON24 | A8 | I | Analog input monitor pin |
| ENABLE PINS | |||
| EN1 | M9 | O | Digital output, rail enable signal |
| EN2 | N9 | O | Digital output, rail enable signal |
| EN3 | L10 | O | Digital output, rail enable signal |
| EN4 | K10 | O | Digital output, rail enable signal |
| EN5 | L9 | O | Digital output, rail enable signal |
| EN6 | K9 | O | Digital output, rail enable signal |
| EN7 | N8 | O | Digital output, rail enable signal |
| EN8 | M8 | O | Digital output, rail enable signal |
| EN9 | L8 | O | Digital output, rail enable signal |
| EN10 | K8 | O | Digital output, rail enable signal |
| EN11 | N7 | O | Digital output, rail enable signal |
| EN12 | M7 | O | Digital output, rail enable signal |
| EN13 | K7 | O | Digital output, rail enable signal |
| EN14 | L7 | O | Digital output, rail enable signal |
| EN15 | N4 | O | Digital output, rail enable signal |
| EN16 | N3 | O | Digital output, rail enable signal |
| EN17 | K3 | O | Digital output, rail enable signal |
| EN18 | K4 | O | Digital output, rail enable signal |
| EN19 | J4 | O | Digital output, rail enable signal |
| EN20 | J2 | O | Digital output, rail enable signal |
| EN21 | J3 | O | Digital output, rail enable signal |
| EN22 | H4 | O | Digital output, rail enable signal |
| EN23 | H3 | O | Digital output, rail enable signal |
| EN24 | G4 | O | Digital output, rail enable signal |
| CLOSED-LOOP MARGIN PINS | |||
| MARGIN1 | J13 | O | Closed-loop margin PWM output |
| MARGIN2 | L5 | O | Closed-loop margin PWM output |
| MARGIN3 | D8 | O | Closed-loop margin PWM output |
| MARGIN4 | K6 | O | Closed-loop margin PWM output |
| MARGIN5 | D4 | O | Closed-loop margin PWM output |
| MARGIN6 | E4 | O | Closed-loop margin PWM output |
| MARGIN7 | F5 | O | Closed-loop margin PWM output |
| MARGIN8 | N5 | O | Closed-loop margin PWM output |
| MARGIN9 | N6 | O | Closed-loop margin PWM output |
| MARGIN10 | K5 | O | Closed-loop margin PWM output |
| MARGIN11 | M6 | O | Closed-loop margin PWM output |
| MARGIN12 | L6 | O | Closed-loop margin PWM output |
| MARGIN13 | D11 | O | Closed-loop margin PWM output |
| MARGIN14 | C12 | O | Closed-loop margin PWM output |
| MARGIN15 | A13 | O | Closed-loop margin PWM output |
| MARGIN16 | B13 | O | Closed-loop margin PWM output |
| MARGIN17 | D12 | O | Closed-loop margin PWM output |
| MARGIN18 | C13 | O | Closed-loop margin PWM output |
| MARGIN19 | E12 | O | Closed-loop margin PWM output |
| MARGIN20 | E13 | O | Closed-loop margin PWM output |
| MARGIN21 | M13 | O | Closed-loop margin PWM output |
| MARGIN22 | L12 | O | Closed-loop margin PWM output |
| MARGIN23 | M5 | O | Closed-loop margin PWM output |
| MARGIN24 | J12 | O | Closed-loop margin PWM output |
| GPIO and CASCADING PINS | |||
| GPIO1 | L4 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO2 | N1 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO3 | M4 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO4 | N2 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO5 | F4 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO6 | F3 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO7 | G3 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO8 | D10 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO9 | L11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO10 | N12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO11 | N11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO12 | M11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO13 | F13 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO14 | F12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO15 | G11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO16 | H10 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO17 | H13 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO18 | H12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO19 | H11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO20 | L13 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO21 | B11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO22 | B12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO23 | C11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| GPIO24 | A12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
| SYNC_CLK | K2 | I/O | Synchronization clock I/O for multiple chip cascading |
| Logic GPO PINS | |||
| LGPO1 | C9 | O | Logic GPO |
| LGPO2 | B9 | O | Logic GPO |
| LGPO3 | A9 | O | Logic GPO |
| LGPO4 | C8 | O | Logic GPO |
| LGPO5 | D5 | O | Logic GPO |
| LGPO6 | C5 | O | Logic GPO |
| LGPO7 | C6 | O | Logic GPO |
| LGPO8 | C4 | O | Logic GPO |
| LGPO9 | L3 | O | Logic GPO |
| LGPO10 | M1 | O | Logic GPO |
| LGPO11 | M2 | O | Logic GPO |
| LGPO12 | M3 | O | Logic GPO |
| PMBus COMM INTERFACE | |||
| PMBUS_CLK | E10 | I | PMBus clock (must pull up to V33D) |
| PMBUS_DATA | D13 | I/O | PMBus data (must pull up to V33D) |
| PMBALERT# | F11 | O | PMBus alert, active-low, open-drain output (must pull up to V33D) |
| PMBUS_CNTRL | E11 | I | PMBus control pin |
| PMBUS_ADDR0 | L2 | I | PMBus digital address input. Bit 0. |
| PMBUS_ADDR1 | L1 | I | PMBus digital address input. Bit 1. |
| PMBUS_ADDR2 | K1 | I | PMBus digital address input. Bit 2. |
| JTAG | |||
| JTAG_TMS | A10 | I | Test mode select with internal pullup |
| JTAG_TCK | C10 | I | Test clock with internal pullup |
| JTAG_TDO | A11 | I/O | Test data out with internal pullup |
| JTAG_TDI | B10 | I/O | Test data in with internal pullup |
| INPUT POWER, GROUND, AND EXTERNAL REFERENCE PINS | |||
| RESET | G10 | I | Active-low device reset input. Pull up to V33D. |
| V33A | D3 | I | Analog 3.3-V supply. It should be decoupled from V33D to minimize the electrical noise contained on V33D from affecting the analog functions. |
| V33D | D7 E6 E8 E9 F10 J7 J9 J10 |
I | Digital 3.3-V supply for I/O and some logic. |
| BPCap | D6 J1 J6 K13 |
I | Positive supply for most of the logic function, including the processor core and most peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO. The BPCap pins should only be connected to each other and an external capacitor as specified in On-Chip Low Drop-Out (LDO) Regulator Characteristics section. |
| AVSS | C3 E3 |
I | Analog ground. These are separated from DVSS to minimize the electrical noise contained on V33D from affecting the analog functions. |
| DVSS | A1 C7 D9 E5 F9 H5 H9 J5 J8 J11 |
I | Ground reference for logic and I/O pins. |
| VREFA+ | D2 | I | (Optional) Positive node of external reference voltage |
| VREFA- | D1 | I | (Optional) Negative node of external reference voltage |
| UNUSED PINS | |||
| UNUSED-NC | A2 G13 M12 N10 |
Do not connect. Leave floating/isolated. | |
| UNUSED-DVSS | G12 K11 M10 N13 |
Tie to DVSS. | |
| UNUSED-V33D | K12 | Tie to V33D. | |