10.1 Layout Guidelines
The thermal pad provides a thermal and mechanical interface between the device and the printed circuit board (PCB). Connect the exposed thermal pad of the PCB to the device VSS pins and provide at least a 4 × 4 pattern of PCB vias to connect the thermal pad and VSS pins to the circuit ground on other PCB layers.
For supply-voltage decoupling, provide power-supply pin bypass to the device as follows:
- 1-μF, X7R ceramic in parallel with 0.01-μF, X7R ceramic at pin 47 (BPCAP)
- 0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 44 (V33DIO2) and 45 (V33D)
- 0.1-μF, X7R ceramic at pin 7 (V33DIO1)
- 0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 46 (V33A)
- Connect V33D (pin 45), V33DIO1 (pin 7) and V33DIO2 (pin 44) to 3.3-V supply directly. Connect V33A (pin 46) to V33D through a 4.99-Ω resistor. This resistor and V33A decoupling capacitors form a low-pass filter to reduce noise on V33A.
Depending on use and application of the various GPIO signals used as digital outputs, some impedance control may be desired to quiet fast signal edges. For example, when using the FPWM pins for voltage margining, the pin is configured as a digital
clock signal. Route these signals away from sensitive analog signals. It is also good design practice to provide a series impedance of 20 Ω to 33 Ω at the signal source to slow the fast-digital edges.