9.2.1.1.1 Gate Input

The input stage of the driver should be driven by a signal with fast rise and fall times. Caution must be exercised whenever the driver is used with slowly varying input signals, in situations where the device is located in a mechanical socket or PCB layout is not optimal (bad grounding, for example). Ground bounce is often caused by high di/dt current from the driver output, coupled with board-layout parasitic. The differential voltage between the input pin IN and ground pad GND may be modified by ground bounce and trigger an unintended change of output state. Because of short propagation delay, the unintended change of state can ultimately result in high-frequency oscillations, which increases power dissipation and can potentially damage the device. In the worst case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1 nF) between the input pin and ground very close to the driver device may be necessary.

9.2.1.1.2 Gate Output

The output of the gate driver (OUT) must be connected as close to the MOSFET gate as possible. A small resistor may be connected in between to reduce the high-frequency oscillations on the gate. Doing so can also slow down the gate transitions. The DTC detection windows inside UCD3138A may need some adjustment to compensate for the delay caused by the added resistor.

9.2.1.1.3 Drain-to-Source Voltage Sensing

When the drain-to-source voltage is below 0 V, current flows out of the VD pin to the drain terminal of the MOSFET. This current flow must be limited to ensure proper operation of the device. The recommended current-limiting resistance value is 20Ω.

The highest voltage that can be applied to VD pin is 45 V which is good for applications where 40-V MOSFETs are used for the secondary-side SRs. If a higher voltage is required for VD pin, an external high-voltage blocking circuit can be used together with the UCD7138 device as shown in Figure 34. Depending on the required voltage rating, a different external high-voltage blocking MOSFET can be selected. Usually a small SOT-23 MOSFET can be used. In this circuit, the gate terminal of the external high-voltage blocking MOSFET is connected to V_CC of the UCD7138 gate driver. The source terminal is connected with a current-limiting resistor to the VD pin of the UCD7138 device. The drain terminal is connected to the SR MOSFET drain terminal. When a low voltage is presented at the drain terminal, the blocking MOSFET is turned on because of the positive gate-to-source voltage. When the drain voltage becomes higher and higher, the source terminal voltage rises along with the drain terminal until the gate-to-source voltage falls below the threshold. When the source voltage is high enough so that the blocking MOSFET is turned off, the high voltage on the SR drain is blocked.

Figure 34. External High-Voltage Blocking Circuit

9.2.1.1.4 DTC Output

The DTC pin is the internal comparator output. This pin should be connected to the DTC0 or DTC1 pin on the UCD3138A device. To keep edges sharp, no filtering is recommended. If noise spikes are observed on the DTC signal, the blanking times in the UCD3138A device can be used to prevent the digital controller from sensing noise. This pin is not designed to drive large current. If filtering must be used, ensure that the sink and source current on this pin is within ±4 mA as specified in the
Electrical Characteristics table.

9.2.1.1.5 Turn-on Edge Optimization

The turnon edge optimization is useful when a positive current flow is at the rising edge of SRs. To maximize the efficiency gain, the dead time between the falling edge of the primary and the rising edge of the secondary should be programmed to a smaller value than expected, so that the rising edge of the SRs can move freely by UCD7138.

9.2.1.2.1 Design Without SR-Control Optimization

The design procedure of an LLC converter with synchronous rectification can be greatly simplified by using the UCD7138 and UCD3138A chipset. The converter hardware and firmware can initially be designed without advanced SR optimization and then add SR optimization function in.

For more information on the UCD3138A-based digital LLC converter, UCD3138A Highly Integrated Digital Controller for Isolated Power, SLUSC66.

9.2.1.2.2 Setting the DTC Detection Window

The body-diode conduction should be detected in a specific region for the system to operate correctly. The detection window is defined by a blanking time register DETECT_BLANK and a detection length register DETECT_LEN in the UCD3138A device. To set the detection window, let the LLC converter operate below resonant frequency. measure the VD, IN, and DTC waveforms on an oscilloscope. Use cursors to measure the time, t, difference between the IN falling edge and the starting point of body-diode conduction (first falling edge of DTC excluding noise spike). The blanking time should be set to be less than t. Usually the required blanking time is very short or non existent, so the blanking time can be set to around 10% of t. The detection window length can be set to a few times of the desired body-diode conduction time. For example, if the desired body-diode conduction time is 40 ns, the detection window length can be set to 120 ns. Make sure that the body-diode conduction is well covered inside the detection window when it is at an optimal value. The end point of the detection window should never exceed the first valley on the VD waveform to avoid errors in measurement (see Figure 35).

Figure 35. Setting the DTC Detection Window in UCD3138A

After the detection window is set, enable the DTC module in manual control mode. Set the offset in the manual control registers to 0. Change the input voltage and load current to different operation points to verify that the UCD3138A DTC module measures the correct values in the A_CNT and B_CNT registers. See the UCD3138A64 Programmer’s Manual, SLUUB54 for detailed register information.

9.2.1.2.3 Setting the Clamps

The SR adjustment accumulator clamps defines the maximum SR turnoff edge offset from the calculated value from the UCD3138A compensator. The maximum clamp can be set to prevent the SR on time from going too long and causing shoot through. The minimum clamp can be set based on the light load condition where the desired SR turnoff edge offset is the maximum.

In addition to the SR adjustment accumulator clamps, the SR pulse falling edge is naturally clamped at 50% or 100% or the switching period in UCD3138A. This natural clamp is a default feature of UCD3138A and does not require any special setting.

9.2.1.2.4 Setting the DTC Optimization Target and Hysteresis

The body diode must maintain a minimum conduction time for the UCD3138A DTC interface to function properly. The minimum body-diode conduction time is set by the DTC target and target register. A target hysteresis register can also be set to reduce the steady-state output-voltage ripple.

9.2.1.2.5 Setting the DTC Negative Current Fault Protection

If the detected body-diode conduction time is less than the programmed threshold, negative current can occur. This threshold can be set by the fault threshold register in the UCD3138A DTC module. If a DTC fault is detected, the SR on time is reduced by a programed step size in the next switching cycle. This step size is defined by FLT_STEP register in the DTC module. To avoid noise and jitter in the negative current fault detection, a consecutive DTC fault counter can be used. A fault step is executed only after a consecutive number of faults are detected.

After all these registers are set, enable the UCD3138A DTC module in automatic control mode, enable the turnon-edge optimization on the UCD7138 device, and review the different operation conditions to see the overall system performance. The DTC module can be turned on or off by toggling DTC_EN bit in Loop Mux register in UCD3138A. The performance before and after SR optimization control can be compared very easily as shown in the Application Curves section.