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SLUSC99A July 2016 – January 2017 UCD3138128A

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PFC|80
- MTQF009B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Pin Configuration and Functions

PFC Package

80 Pins (TQFP)

Top View

Additional pin functionality is specified in the following table.

Pin Functions

PIN	NAME	PRIMARY ASSIGNMENT	ALTERNATE ASSIGNMENT		CONFIGURABLE AS A GPIO?
PIN	NAME	PRIMARY ASSIGNMENT	NO. 1	NO. 2	CONFIGURABLE AS A GPIO?
1	AD13	12-bit ADC, Ch 13, comparator E, I-share	DAC output
2	AD12	12-bit ADC, Ch 12
3	AD10	12-bit ADC, Ch 10
4	AD07	12-bit ADC, Ch 7, Connected to comparator F and reference to comparator G	DAC output
5	AD06	12-bit ADC, Ch 6, Connected to comparator F	DAC output
6	AD04	12-bit ADC, Ch 4, Connected to comparator D	DAC output
7	AD03	12-bit ADC, Ch 3, Connected to comparator B and C
8	V33DIO	Digital I/O 3.3V core supply
9	DGND	Digital ground
10	RESET	Device Reset Input, active low
11	PWM2	General purpose PWM 2			Yes
12	PWM3	General purpose PWM 3			Yes
13	TCAP1	Timer Capture Input	TCAP0		Yes
14	ADC_EXT_TRIG	ADC conversion external trigger input			Yes
15	PMBUS_CLK	PMBUS Clock (Open Drain)			Yes
16	PMBUS_DATA	PMBus data (Open Drain)			Yes
17	PMBUS_ALERT	PMBus Alert (Open Drain)			Yes
18	PMBUS_CTRL	PMBus Control (Open Drain)			Yes
19	I2C_CLK	I2C Clock			Yes
20	I2C_DATA	I2C Data			Yes
21	DGND	Digital ground
22	DPWM0A	DPWM 0A output			Yes
23	DPWM0B	DPWM 0B output			Yes
24	DPWM1A	DPWM 1A output			Yes
25	DPWM1B	DPWM 1B output			Yes
26	DPWM2A	DPWM 2A output			Yes
27	DPWM2B	DPWM 2B output			Yes
28	DPWM3A	DPWM 3A output			Yes
29	DPWM3B	DPWM 3B output			Yes
30	DTC0	Synchronous Rectifier dead time optimization control input 0	GPIOA		Yes
31	DTC1	Synchronous Rectifier dead time optimization control input 1	GPIOB		Yes
32	GPIOC	General purpose IO C			Yes
33	GPIOD	General purpose IO D			Yes
34	SYNC	DPWM Synchronize pin			Yes
35	SCI_TX0	SCI TX 0			Yes
36	SCI_RX0	SCI RX 0			Yes
37	SCI_TX1	SCI TX 1			Yes
38	SCI_RX1	SCI RX 1			Yes
39	PWM0	General purpose PWM 0	SYNC		Yes
40	PWM1	General purpose PWM 1			Yes
41	DGND	Digital ground
42	EXT_INT	External Interrupt			Yes
43	FAULT0	External fault input 0			Yes
44	FAULT1	External fault input 1			Yes
45	TCK⁽¹⁾	JTAG test clock. It is recommended that this pin is pulled LOW on the target.	RTC_IN	XTAL_CLK_OUT	Yes
46	TDO⁽¹⁾	JTAG test data output. It is recommended that this pin is pulled HIGH on the target.	TCAP0	TCAP1	Yes
47	TDI⁽¹⁾	JTAG test data input. It is recommended that this pin is pulled HIGH on the target.	TCAP0	TCAP1	Yes
48	TMS⁽¹⁾	JTAG test mode select. This pin must be pulled HIGH on the target so that the effect of any spurious TCKs when there is no connection is benign.			Yes
49	TCAP0	Timer Capture Input	TCAP1		Yes
50	SPI_CS	SPI Chip Select			Yes
51	SPI_CLK	SPI Clock			Yes
52	SPI_MOSI	SPI Master Output Slave Input			Yes
53	SPI_MISO	SPI Master Input Slave Output			Yes
54	FAULT2	External fault input 2			Yes
55	FAULT3	External fault input 3			Yes
56	DGND	Digital ground
57	V33DIO	Digital I/O 3.3-V core supply
58	BP18	1.8V Bypass (For internal use only, do not load)
59	V33D	Digital 3.3-V core supply
60	DGND	Digital ground
61	XTAL_OUT	Crystal oscillator input
62	XTAL_IN	Crystal oscillator output
63	AGND	Analog ground
64	EAP0	Channel #0, differential analog voltage, positive input
65	EAN0	Channel #0, differential analog voltage, negative input
66	EAP1	Channel #1, differential analog voltage, positive input
67	EAN1	Channel #1, differential analog voltage, negative input
68	EAP2	Channel #2, differential analog voltage, positive input
69	EAN2	Channel #2, differential analog voltage, negative input
70	AGND	Analog ground
71	V33A	Analog 3.3V supply
72	AD00	12-bit ADC, Ch 0, Connected to current source
73	AD01	12-bit ADC, Ch 1, Connected to current source
74	AD02	12-bit ADC, Ch 2, Connected to comparator A, I-share
75	AD05	12-bit ADC, Ch 5
76	AD14	12-bit ADC, Ch 14
77	AD08	12-bit ADC, Ch 8
78	AD09	12-bit ADC, Ch 9
79	AD11	12-bit ADC, Ch 11
80	AGND	Analog ground

(1) Fusion Digital Power based debug tools are recommended instead of JTAG.