DESAT protection prevents the power transistor from damage in case of short circuit faults. The DESAT input monitors the VCEsat (IGBT)/VDSon (MOSFET) through an external resistor and diode network (R1, C1, D1 and D2 in Figure 7-16). The D1 diode protects the driver IC from high voltage when the power transistor is OFF. The resistor, R1, limits the negative voltage applied on the DESAT input during switching transitions. While the power FET is ON, an internal current source, I_CHG, forward biases the DESAT diode and dumps into the collector/drain of the external power switch. Under normal conditions, the V_CEsat/V_DSon is less than a few volts, however, during short circuit faults the V_CEsat/V_DSon may rise up to the DC bus voltage when the power transistor operates in the linear region. In this situation, the D1 diode is reverse biased, so the internal current source charges the blanking capacitor (C1) Once the voltage on the DESAT input charges up to the selected threshold (V_DESATth),the driver output is pulled into the safe state defined by the CFG10[FS_STATE_DESAT_SCP] bit (CFG10), the fault is indicated in the STATUS3[DESAT_FAULT] (STATUS3), and, if unmasked, the NFLT1 output pulls low. The turn-off of the driver output during a DESAT fault is selectable between normal, soft turn-off (STO), or two-level turnoff (2LTO) dictated by the CFG5[2LTOFF_STO_EN] bits (CFG5). See the Section 7.3.5.9and Section 7.3.5.8 for additional details on STO and 2LTO, respectively. The blanking capacitor is fully discharged at the falling edge of the PWM signal using the internal discharge current (I_DCHG). In addition to the blanking time, DESAT is deglitched to prevent false triggering during transitions. The deglitch is selectable using the CFG4[DESAT_DEGLITCH] bit (CFG4).

The DESAT threshold is selectable using the CFG5[DESATTH] bits (CFG5), and the DESAT charging current (I_CHG) is selectable, using the CFG5[DESAT_CHG_CURR] bits (CFG5), to control the blanking time (t_{DS_BLK}). The discharge current is enabled/disabled using the CFG5[DESAT_DCHG_EN] bit (CFG5). The DESAT protection function is enabled or disabled using the CFG4[DESAT_EN] bit (CFG4). The implementation diagram and timing schemes of DESAT based short circuit protection are presented in Figure 7-16 and Figure 7-17 respectively. See the Section 8.3.1.1section for details on selecting the R1, C1, and D1 values.

Figure 7-16 Block diagram of implementation of DESAT protection function.

Figure 7-17 Timing scheme of implementation of DESAT protection function (safe state is LOW).