The UCC57142 device provides an undervoltage lockout threshold of 12V and the UCC57148 device provides an undervoltage lockout threshold of 8V. The UVLO hysteresis range helps to avoid any chattering due to the presence of noise on the bias supply. 1V of typical UVLO hysteresis is expected. 2 μs of turnon delay is expected due to the UVLO feature during startup or when the supply voltage exceeds the rising thresholds. The UVLO turn-off delay is also minimized as much as possible to 3 μs maximum. The UVLO delay is designed to minimize chattering that may occur due to very fast transients that may appear on VDD. When the bias supply is below UVLO thresholds, the outputs are held actively low irrespective of the state of the input pins. When exiting the UVLO, the EN/FLT is charged by external pullup circuit. The fault clear time is depended on the time constant of the R_FLTC and C_FLTC. After exit the UVLO longer than the fault clear time and UVLO turn on delay, the OUT follow the IN after the first rising edge of the IN.

Figure 7-2 UVLO Timing Diagram