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SLVSJ11 August 2025 UCC57132 , UCC57138

PRODUCTION DATA

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

5.5 Electrical Characteristics

VDD = 15 V, VEE = 0 V, 1-μF capacitor from VDD to COM, 1-μF capacitor from VEE to COM, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_VDDQ	VDD quiescent supply current	V_IN = 3.3 V, EN = 5V, VDD = 6.5 V			1.3	mA
I_VDD	VDD static supply current	V_IN = 3.3 V, EN = 5 V		0.7	1.5	mA
I_VDD	VDD static supply current	V_IN = 0 V, EN = 5 V		0.7	1.1	mA
I_VEEQ	VEE static supply current	V_IN = 0 V, EN = 5 V, VEE = -10 V			1.1	mA
I_VDDO	VDD dynamic operating current	f_SW = 1MHz, EN = 5 V, VDD=15 V, C_L=1.8 nF			30	mA
I_DIS	VDD disable current	V_IN = 3.3 V, EN = 0 V		0.8	1.1	mA
VDD UNDERVOLTAGE THRESHOLDS AND DELAY
V_{VDD_ON}	VDD UVLO Rising Threshold	8 V UVLO Option	7.65	8	8.35	V
V_{VDD_OFF}	VDD UVLO Falling Threshold		6.65	7	7.35	V
V_{VDD_HYS}	VDD UVLO Threshold Hysteresis			1		V
t_UVLO2FLT	Propagation delay from UVLO to FLT			2		μs
V_{VDD_ON}	VDD UVLO Rising Threshold	12 V UVLO Option	12.8	13.5	14.2	V
V_{VDD_OFF}	VDD UVLO Falling Threshold		11.8	12.5	13.2	V
V_{VDD_HYS}	VDD UVLO Threshold Hysteresis			1		V
IN, EN/FLT
V_INH	Input High Threshold Voltage		1.8	2.2	2.6	V
V_INL	Input Low Threshold Voltage		0.8	1.2	1.6	V
V_{IN_HYS}	Input-threshold Hysteresis			1		V
R_IND	IN Pin Pull Down Resistance			115		kΩ
V_ENH	Enable High Threshold Voltage		1.8	2.2	2.6	V
V_ENL	Enable Low Threshold Voltage		0.8	1.2	1.6	V
V_{EN_HYS}	Enable Threshold Hysteresis			1		V
R_ENU	EN Pin Pull Up Resistance			2		MΩ
I_FLTth	FLT threshold	V_FLT-sink = 400 mV, Tj=25 °C	18			mA
OC DETECTION
V_OCTH	OC detection threshold, referenced to GND (UCC5713X)	500 mV option	474	500	526	mV
V_OCTL	OC release threshold, referenced to GND (UCC5713X)	500 mV option	463	488	513	mV
t_OCFIL⁽¹⁾	OC deglitch filter ( 8V-UVLO version)			70		ns
t_OCFIL⁽¹⁾	OC deglitch filter (12V-UVLO version)			190		ns
t_OC2OUT⁽¹⁾	OC propagation delay to 90% of OUT (8V-UVLO version)			115	145	ns
t_OC2OUT⁽¹⁾	OC propagation delay to 90% of OUT (12V-UVLO version)			230	350	ns
t_OC2FLT⁽¹⁾	OC propagation delay to 90% of EN/FLT low(8V-UVLO version)			115	150	ns
t_OC2FLT⁽¹⁾	OC propagation delay to 90% of EN/FLT low(12V-UVLO version)			220	320	ns
t_OCLEB⁽¹⁾	OC Leading edge blanking time( 8V-UVLO version)			60	80	ns
t_OCLEB⁽¹⁾	OC Leading edge blanking time( 12V-UVLO version)			180	250	ns
OVERTEMPERATURE PROTECTION
T_SD⁽¹⁾	Overtemperature threshold			180		℃
T_HYS⁽¹⁾	Overtemperature protection hysteresis			30		℃
t_OTP2FLT⁽¹⁾	Propagation delay from overtemperature shutdown to FLT	Over temperature shutdown to 90% of FLT, Cl=10 pF		8		us
OUTPUT DRIVER STAGE
I_SRCPK⁽¹⁾	Peak Output Source Current	C_VDD = 10 μF, C_L = 0.1 μF, f = 1 kHz		-3		A
I_SNKPK⁽¹⁾	Peak Output Sink Current	C_VDD = 10 μF, C_L = 0.1 μF, f = 1 kHz		3		A
R_OH	Pull up resistance	I_OUT = –500 mA		5		Ω
R_OL	Pull down resistance	I_OUT = 50 mA		1		Ω

(1) Parameter are not tested in production