ZHCSU66J August 2001 – December 2023 UCC29002 , UCC39002
PRODUCTION DATA
- 1
- 1特性
- 2應(yīng)用
- 3說明
- 4Pin Configuration and Functions
- 5Specifications
-
6Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Differential Current-Sense Amplifier (CS+, CS?, CSO)
- 6.3.2 Load-Share Bus Driver Amplifier (CSO, LS)
- 6.3.3 Load-Share Bus Receiver Amplifier (LS)
- 6.3.4 Error Amplifier (EAO)
- 6.3.5 Adjust Amplifier Output (ADJ)
- 6.3.6 Enable Function (CS+, CS?)
- 6.3.7 Fault Protection on LS Bus
- 6.3.8 Start-Up and Adjust Logic
- 6.3.9 Bias Input and Bias_OK Circuit (VDD)
- 6.4 Device Functional Modes
- 7Application and Implementation
- 8Device and Documentation Support
- 9Revision History
- Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
6.3.7 Fault Protection on LS Bus
Accidentally, the load-share bus might be short-circuited to the positive bias voltage of the UCC29002 device or to ground. These events can result in erroneous output voltage adjustment. For that reason, the LS bus voltage is continuously monitored by a window comparator as shown in Figure 6-2. An LS-bus FAULT condition is asserted if either [ VLS > (VVDD - 0.7 V) ] or [ VLS < (2/3 × VCSO) ] is true.
Figure 6-2 LS Bus
Fault Protection ComparatorsThe LS-bus FAULT signal is handled by the Start-Up and Adjust Logic block to affect the UCC29002 operating mode. If the FAULT signal is asserted true, the UCC29002 is disabled.