ZHCSK44G December 2009 – November 2022 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Custom Design With WEBENCH? Tools
- 9.2.2.2 Input Bulk Capacitor and Minimum Bulk Voltage
- 9.2.2.3 Transformer Turns Ratio and Maximum Duty CycleG
- 9.2.2.4 Transformer Inductance and Peak Currents
- 9.2.2.5 Output Capacitor
- 9.2.2.6 Current Sensing Network
- 9.2.2.7 Gate Drive Resistor
- 9.2.2.8 VREF Capacitor
- 9.2.2.9 RT/CT
- 9.2.2.10 Start-Up Circuit
- 9.2.2.11 Voltage Feedback Compensation
- 9.2.3 Application Curves
- 9.2.4 Power Supply Recommendations
- 9.2.5 Layout
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
8.3.6 Oscillator Synchronization
Synchronization is best achieved by forcing the timing capacitor voltage above the oscillator's internal upper threshold. A small resistor is placed in series with CCT to GND. This resistor serves as the input for the sync pulse which raises the CCT voltage above the oscillator’s internal upper threshold. The PWM is allowed to run at the frequency set by RRT and CCT until the sync pulse appears. This scheme offers several advantages including having the local ramp available for slope compensation. The UCC28C4x-Q1 oscillator must be set to a lower frequency than the sync pulse stream, typically 20 percent with a 0.5-V pulse applied across the resistor.
Figure 8-5 Oscillator Synchronization Circuit