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SLUS769D July 2013 – December 2016 UCC28910 , UCC28911

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

D|7
- MPDS347D

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

9 Specifications

9.1 Absolute Maximum Ratings

(unless otherwise noted) ⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_DRAIN	DRAIN voltage	Internally limited⁽³⁾	700	V
I_DRAIN	Negative drain current	–100		mA
V_DD	Supply voltage		Internally limited⁽³⁾	V
I_VDD(clp)	Maximum VDD clamp current		10	mA
V_VS	Voltage range	Internally limited⁽³⁾	7	V
V_IPK	Voltage range	−0.5	5.0	V
I_VS	Peak VS pin current (current out of the pin)	−1.2		mA
I_DRAIN	Pulsed drain current⁽⁴⁾, UCC28910		950	mA
I_DRAIN	Pulsed drain current⁽⁴⁾, UCC28911		1200	mA
T_LEAD	Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds		260	°C
T_J	Operating junction temperature range	−55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified pin. These ratings apply over the operating ambient temperature ranges unless otherwise noted.

(3) Do not drive with low impedance voltage source.

(4) Maximum pulse width = 100 μs.

9.2 Storage Conditions

		MIN	MAX	UNIT
T_stg	Storage temperature	−65	150	°C

9.3 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

9.4 Recommended Operating Conditions⁽¹⁾⁽²⁾

			MIN	NOM	MAX	UNIT
V_VDD	Voltage on VDD terminal during operation		VDD_OFF		V_VDD(clp)	V
I_VS	Current out of the terminal				1	mA
I_{D(peak_max)}	Maximum drain peak current	UCC28910		600		mA
I_{D(peak_max)}	Maximum drain peak current	UCC28911		700		mA
T_J	Operating junction temperature		-40		125	°C

(1) Unless otherwise noted, all voltages are with respect to GND.

(2) In case of thermal shut down, if T_A > 100°C, the device does not restart because of the T_J(hys) Electrical Characteristics.

9.5 Thermal Information

THERMAL METRIC⁽¹⁾		UCC28910	UCC28911	UNITS
		D	D
		7 Pin SOIC	7 Pin SOIC
θ_JA	Junction-to-ambient thermal resistance	102.2	102.2	°C/W
θ_JCtop	Junction-to-case (top) thermal resistance	39.1	39.1
θ_JB	Junction-to-board thermal resistance	54.7	54.7
ψ_JT	Junction-to-top characterization parameter	5.4	5.4
ψ_JB	Junction-to-board characterization parameter	54.7	54.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

9.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted), V_VDD = 15 V, T_A = -40°C to 125°C, T_A = T_J

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY INPUT
I_RUN	Supply current, run	V_VS = 3.9 V, f_SW = f_SW(max)	UCC28910	2.3	2.9	3.4	mA
I_RUN	Supply current, run	V_VS = 3.75 V, f_SW = f_SW(max)	UCC28911	2.3	2.9	3.4	mA
I_RUNQ	Quiescent supply current	V_VS = 3.9 V, f_SW = 0 Hz	UCC28910	1.90	2.35	2.80	mA
I_RUNQ	Quiescent supply current	V_VS = 3.75 V, f_SW = f_SW_(max)	UCC28911	1.90	2.35	2.80	mA
I_WAIT	Wait supply current	V_VS = 4.1 V, f_SW = f_SW(min), T_J = 25°C	UCC28910		270	370	µA
I_WAIT	Wait supply current	V_VS = 4.1 V, f_SW = f_SW(min), T_J = 25°C	UCC28911		250	330	µA
I_WAITQ	Quiescent wait supply current	V_VS = 4.1 V, f_SW = 0 Hz, T_J = 25°C	UCC28910		200	280	µA
I_WAITQ	Quiescent wait supply current	V_VS = 4.1 V, f_SW = 0 Hz, T_J = 25°C	UCC28911		190	240	µA
I_START	Supply current before start	0 V ≤ V_VDD ≤ 5.6 V, V_DRAIN = 0 V	UCC28910		65	90	µA
I_START	Supply current before start	0 V ≤ V_VDD ≤ 5.6 V, V_DRAIN = 0 V, T_J = 25°C	UCC28911		65	80	µA
I_FAULT	Supply current after fault	f_SW = 0 Hz	UCC28910		190	260	µA
I_FAULT	Supply current after fault	f_SW = 0 Hz, T_J = 25°C	UCC28911		190	240	µA
UNDER-VOLTAGE LOCKOUT
VDD_ON	VDD turn-on threshold	V_VDD low to high		9.0	9.5	10.0	V
VDD_OFF	VDD turn-off threshold	V_VDD high to low		6.0	6.5	7.0	V
VDD_HV(on)	HV current source start	V_VDD high to low		4.8	5.2	5.6	V
ΔV_UVLO	UVLO hysteresis	VDD_ON – VDD_OFF		2.8	3.0	3.2	V
STARTUP CURRENT SOURCE
I_CH1	Startup current with VDD shorted to GND	V_VDD < 250 mV, V_DRAIN = 100 V		–300		–100	µA
I_CH2	Sourced current for startup at high VDD	V_VDD = 8 V, V_DRAIN = 100 V		–9.75		–0.40	mA
I_CH3	Sourced current for startup at low VDD	V_VDD = 2 V, V_DRAIN = 100 V		–13.75		–1.30	mA
VS INPUT
V_VSR	Regulating level	Measured in no load condition, T_J = 25°C		4.01	4.05	4.09	V
V_VSNC	Negative clamp level	I_VS = –300 μA		–190	–250	–325	mV
I_VS	Input bias current	V_VS = 4 V		–0.25	0.00	0.25	µA
PROTECTION
I_D(ocp)	DRAIN over current	I_PK pin shorted to GND	UCC28910	725	850	925	mA
I_D(ocp)	DRAIN over current	I_PK pin shorted to GND	UCC28911	880	980	1090	mA
V_{CSTE_OCP}	Equivalent V_CST(OCP), I_D(ocp) x R_IPK	V_VS = 3.9 V	UCC28910	670	770	830	V
V_{CSTE_OCP}	Equivalent V_CST(OCP), I_D(ocp) x R_IPK	V_VS = 3.75 V	UCC28911	800	885	975	V
V_{CSTE_OCP2}	Equivalent V_CST(OCP2) I_D(ocp2) x R_IPK	V_VS = 3.9 V	UCC28910		1200		V
V_{CSTE_OCP2}	Equivalent V_CST(OCP2) I_D(ocp2) x R_IPK	V_VS = 3.75 V	UCC28911		1400		V
t_ONMAX(max)	Maximum FET on time at high load	V_VS < 3.9 V, I_PK shorted to GND	UCC28910	13	18	24	µs
t_ONMAX(max)	Maximum FET on time at high load	V_VS = 3.75 V, I_PK shorted to GND	UCC28911	13	18	24	µs
t_ONMAX(min)	Maximum FET on time at low load	V_VS > 4.1 V, I_PK shorted to GND	UCC28910	4.3	6	10	µs
t_ONMAX(min)	Maximum FET on time at low load	V_VS = 4.35 V, I_PK shorted to GND	UCC28911	4.3	6	10	µs
V_OVP	Over-voltage threshold	At VS input, T_J = 25°C		4.45	4.60	4.75	V
I_VSL(run)	VS line sense run current	Current out of VS pin – increasing		175	215	260	µA
I_VSL(stop)	VS line sense stop current	Current out of VS pin – decreasing		60	75	100	µA
K_VSL	Line sense I_VS ratio	I_VSL(run) / I_VSL(stop)		2.55	2.70	2.90	A/A
VDD_CLP	VDD voltage clamp	I_VDDCLP forced = 2 mA		26	28	30	V
I_{VDDCLP_OC}	VDD clamp over current	V_VDD > 25 V		4.65	6.00	7.65	mA
T_J(stop)	Thermal shutdown temperature	Internal junction temperature			150		°C
T_J(hys)	Thermal shutdown hysteresis	Internal junction temperature			50		°C
POWER FET
BV_DSS	Break-down voltage	T_J = 25°C		700			V
R_DS(on)	Power FET on resistance	I_D = 150 mA, T_J = 25°C	UCC28910		10.5	12.0	Ω
		I_D = 150 mA, T_J = 25°C	UCC28911		6.25	7.2	Ω
		I_D = 150 mA, T_J = 125°C	UCC28910		18.4	21.5	Ω
		I_D = 150 mA, T_J = 125°C	UCC28911		11.4	13.4	Ω
I_LEAKAGE	DRAIN pin leakage current	V_DS = 400 V HV, VS = 4.2 V DC T_J = 25°C				10	µA
		V_DS = 400 V HV, VS = 4.2 V DC T_J = 125°C				20	µA
		V_DS = 700 V HV, VS = 4.2 V DC T_J = 25°C				10	µA
CURRENTS
I_{D_PEAK(max)}	Maximum DRAIN peak current	IPK pin shorted to GND, T_J = 25°C	UCC28910	582	600	618	mA
I_{D_PEAK(max)}	Maximum DRAIN peak current	IPK pin shorted to GND, T_J = 25°C	UCC28911	680	700	720	mA
R_{IPK_SHORT}	IPK to GND resistance Max to assume IPK shorted to GND					200	Ω
R_IPK(min)	IPK to GND minimum resistance			900			Ω
V_CSTE(max)	Equivalent current sense threshold, I_{D_PK(max)} × R_IPK	V_VS = 3.9 V, T_J = 25°C	UCC28910	532	540	548	V
V_CSTE(max)	Equivalent current sense threshold, I_{D_PK(max)} × R_IPK	V_VS = 3.75 V	UCC28911	620	630	640	V
V_CSTE(min)	Equivalent current sense threshold, I_{D_PK(min)} × R_IPK	V_VS = 4.1 V	UCC28910	160	180	200	V
V_CSTE(min)	Equivalent current sense threshold, I_{D_PK(min)} × R_IPK	V_VS = 4.35 V	UCC28911	170	216	265	V
K_AM	AM control ratio	V_CSE(max) / V_CSE(min)		2.30	3.00	3.50	V/V
K_CC	CC regulation gain, t_DEMAG × f_SW	V_VS < 3.9 V	UCC28910		0.413
K_CC	CC regulation gain, t_DEMAG × f_SW	V_VS = 3.75 V	UCC28911		0.413
V_CCR	CC regulation constant, V_CSET(max) × K_CC	V_VS < 3.9 V, T_J = 25°C	UCC28910	216	223	230	V
V_CCR	CC regulation constant, V_CSET(max) × K_CC	V_VS < 3.9 V, T_J = 25°C	UCC28911	250	260	270	V

9.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
TIMING
f_SW(max)	Maximum switching frequency	V_VS< 3.9 V	UCC28910	105	115	125	kHz
f_SW(max)	Maximum switching frequency	V_VS= 3.75 V	UCC28911	105	115	125	kHz
f_SW(min)	Minimum switching frequency	V_VS > 4.1 V	UCC28910	360	420	490	Hz
f_SW(min)	Minimum switching frequency	V_VS = 4.35 V	UCC28911	360	420	500	Hz
t_ZTO	Zero crossing timeout delay	V_VS < 3.9 V	UCC28910	1.80	2.10	2.65	µs
t_ZTO	Zero crossing timeout delay	V_VS = 4.35 V	UCC28911	1.80	2.10	2.75	µs
t_ON(min)	Minimum on time	I_PK = 0.85 V	UCC28910		390		ns
t_ON(min)	Minimum on time	I_PK = 0.85 V	UCC28911		420		ns