7.2.1 Terminal Components

Table 1. Terminal Components

PIN		I/O	DESCRIPTION (1)(2)
NAME	NO.
CS	3	I	Equation 1. Equation 2. where: IP(1) is the peak primary current at low line, full load (2) IP(2) is the peak primary current at high line, full load (2) ICS(1) is the power limit current that is sourced at the CS pin at low-line voltage (2) ICS(2) is the power limit current that is sourced at the CS pin at high-line voltage (2) VPL is the Power Limit (PL) threshold (1) VCS(os) is the CS offset voltage (1)
FB	2	I	Opto-isolator collector
GND	4	–	Bypass capacitor to VDD, CBP = 0.1 μF
OUT	5	O	Power MOSFET gate
OVP	7	I	Equation 3. Equation 4. where: IOVP(line) is OVPline current threshold (1) VBULK(ov) is the allowed input over- voltage level (2) VOVP(load) is OVPload(1) VOUT(shutdown) is the allowed output over-voltage level (2) VF is the forward voltage of the secondary rectifier NB is the number of turns on the bias winding (2) NS is the number of turns on the secondary windings (2) NP is the number of turns on the primary windings (2)
SS	1	I	Equation 5. where tSS(min) is the greater of: Equation 6. or Equation 7. RLOAD(ss) is the effective load impedance during soft-start (2) ΔVOUT(step) is the allowed change in VOUT due to a load step (2) POUT(max limit) Programmed power limit level, in W (2) ACS(FB) is the current sense gain (1) VCS(os) is the CS offset voltage (1) ISS is the soft-start charging current (1) VPL is the power limit threshold (1)
STATUS	8	O	Equation 8. Equation 9. where: βSAT is the gain of transistor QST in saturation VBE(sat) is the base-emitter voltage of transistor QST in saturation VDD(uvlo-on) is the start-up threshold (1) ICC is the collector current of QST ISTATUS(leakage) is the maximum leakage/off current of the STATUS pin (1) VBE(off) is the maximum allowable voltage across the base emitter junction that will not turn QST on RDS(on) is the RDS(on) of STATUS (1)
VDD	6	I	CVDD is the greater of: Equation 10. or Equation 11. Equation 12. Equation 13. where: IDD is the operating current of the UCC28600 (1) CISS is the input capacitance of MOSFET M1 VOUT(hi) is VOH of the OUT pin, either 13 V (typ) VOUT clamp or less as measured fQR(max) is fS at high line, maximum load (1) TBURST is the measured burst mode period ΔVDD(burst) is the allowed VDD ripple during burst mode ΔVDD(uvlo) is the UVLO hysteresis (1) VDS1(os) is the amount of drain-source overshoot voltage LLEAKAGE is the leakage inductance of the primary winding CD is the total drain node capacitance of MOSFET M1 ISTARTUP is IDD start-up current of the UCC28600 (1) CSNUB is the snubber capacitor value tSS is the soft start charge time (2)

(1) Refer to the Electrical Characteristics for constant parameters.

(2) Refer to the UCC28600 Design Calculator (SLVC104) or laboratory measurements for currents, voltages and times in the operational circuit.

7.3.1 Oscillator

The oscillator, shown in Figure 8, is internally set and trimmed so it is clamped by the circuit in Figure 8 to a nominal 130-kHz maximum operating frequency. It also has a minimum frequency clamp of 40 kHz. If the FB voltage tries to drive operation to less than 40 kHz, the converter operates in green mode.

Figure 8. Oscillator Details

7.3.2 Status

The STATUS pin is an open drain output, as shown in Figure 10. The status output goes into the OFF-state when FB falls below 0.5 V and it returns to the ON-state (low impedance to GND) when FB rises above 1.4 V. This pin is used to control bias power for a PFC stage, as shown in Figure 9. Key elements for implementing this function include Q1, R_ST1 and R_ST2, as shown in Figure 9. Resistors R_ST1 and R_ST2 are selected to saturate Q1 when it is desirable for the PFC to be operational. During green mode, the STATUS pin becomes a high impedance and R_ST2 causes Q1 to turn-OFF, thus saving bias power. If necessary, use a Zener diode and a resistor (D_Z1 and R_VCC) to maintain VCC in the safe operating range of the PFC controller.

This added stage is required to isolate the STATUS circuitry from the start-up resistor, R_SU, to ensure there is no conduction through STATUS when VDD is below the UVLO turn-on threshold.

7.3.3 Fault Logic

Advanced logic control coordinates the fault detections to provide proper power supply recovery. This provides the conditioning for the thermal protection. Line overvoltage protection (line OVP) and load OVP are implemented in this block. It prevents operation when the internal reference is below 4.5 V. If a fault is detected in the thermal shutdown, line OVP, load OVP, or REF, the UCC28600 undergoes a shutdown/retry cycle.

Refer to the fault logic diagram in Figure 10 and the QR detect diagram in Figure 7 to program line OVP and load OVP. To program the load OVP, select the R_OVP1 – R_OVP2 divider ratio to be 3.75 V at the desired output shut-down voltage. To program line OVP, select the impedance of the R_OVP1 – R_OVP2 combination to draw 450 μA when the V_OVP is 0.45 V during the ON-time of the power MOSFET at the highest allowable input voltage.

7.3.4 Protection Features

The UCC28600 has many protection features that are found only on larger, full featured controllers. Refer to the Functional Block Diagram, Typical Application Diagram, Figure 6, Figure 7, Figure 8, Figure 10, Figure 11, and Figure 12 for detailed block descriptions that show how the features are integrated into the normal control functions.

7.3.5 Overtemperature

Overtemperature lockout typically occurs when the substrate temperature reaches 140°C. Retry is allowed if the substrate temperature reduces by the hysteresis value. Upon an overtemperature fault, C_SS on softstart is discharged and STATUS is forced to a high impedance.

7.3.6 Cycle-by-Cycle Power Limit

The cycle terminates when the CS voltage plus the power limit offset exceeds 1.2 V.

In order to have power limited over the full line voltage range of the QR Flyback converter, the CS pin voltage must have a component that is proportional to the primary current plus a component that is proportional to the line voltage due to predictable switching frequency variations due to line voltage. At power limit, the CS pin voltage plus the internal CS offset is compared against a constant 1.2-V reference in the PWM comparator. Thus during cycle-by-cycle power limit, the peak CS voltage is typically 0.8 V.

The current that is sourced from the OVP pin (I_LINE) is reflected to a dependent current source of ½ I_LINE, that is connected to the CS pin. The power limit function can be programmed by a resistor, R_PL, that is between the CS pin and the current sense resistor. The current, I_LINE, is proportional to line voltage by the transformer turns ratio N_B/N_P and resistor R_OVP1. Current I_LINE is programmed to set the line over voltage protection. Resistor R_PL results in the addition of a voltage to the current sense signal that is proportional to the line voltage. The proper amount of additional voltage has the effect of limiting the power on a cycle-by-cycle basis. Note that R_CS, R_PL, R_OVP1 and R_OVP2 must be adjusted as a set due to the functional interactions.

7.3.7 Primary Current Protection

When the primary current exceeds maximum current level which is indicated by a voltage of 1.25 V at the CS pin, the device initiates a shutdown. Retry occurs after a UVLO_OFF or UVLO_ON cycle. Because the device will initiate cycle-by-cycle power limit first, primary side current protection is not intended to protect against output short circuit conditions. However, this feature does protect the MOSFET against extreme conditions such as transformer saturation.

7.3.8 Over-Voltage Protection

Line and load over voltage protection is programmed with the transformer turn ratios, R_OVP1 and R_OVP2. The OVP pin has a 0-V voltage source that can only source current; OVP cannot sink current.

Line over voltage protection occurs when the OVP pin is clamped at 0 V. When the bias winding is negative, during OUT = HI or portions of the resonant ring, the 0-V voltage source clamps OVP to 0 V and the current that is sourced from the OVP pin is mirrored to the Line_OVP comparator and the QR detection circuit. The Line_OVP comparator initiates a shutdown-retry sequence if OVP sources any more than 450 μA.

Load-over voltage protection occurs when the OVP pin voltage is positive. When the bias winding is positive, during demagnetization or portions of the resonant ring, the OVP pin voltage is positive. If the OVP voltage is greater than 3.75 V, the device initiates a shutdown. Retry occurs after a UVLO_OFF or UVLO_ON cycle.

7.3.9 Undervoltage Lockout

Protection is provided to guard against operation during unfavorable bias conditions. Undervoltage lockout (UVLO) always monitors VDD to prevent operation below the UVLO threshold.

7.4.1 Quasi-Resonant and DCM Control

During this control mode, the rising edge of OUT will occur just after the valley of the resonant ring when the transformer is fully demagnetized. Resonant valley switching is an integral part of QR operation. In this mode, the flyback converter operates at the boundary of discontinuous conduction mode and continuous conduction mode. By adjusting both the peak current and the switching frequency, the output power is adjusted to match the load requirement. When the load increases, the peak current increases and the switching frequency decreases. The minimum switching frequency of the converter is limited to 40 kHz. The transformer magnetizing inductor value has to be designed accordingly so that the converter can deliver the maximum required power while maintaining a switching frequency that is greater than the f_QR(min) over the entire input operating range.

As the load decreases from its designed maximum output power, the UCC28600 will demand a higher switching frequency and decreased peak current. The converter’s maximum switching frequency will be limited to 130 kHz. At this maximum switching frequency, the converter enters DCM control. At DCM control, the peak current is adjusted to control the output power. Slight frequency dithering between resonant valleys will occur as the valley detection is active in DCM control.

Quasi-resonant (QR) and DCM operation occur for feedback voltages, V_FB, between 2.0 V and 3.0 V. In turn, the peak CS voltage is commanded to be between 0.4 V and 0.8 V. The CS pin has an internal dependent current source, 1/2 I_LINE. This current source adds a proportional step offset (power limit offset) to the CS signal and is part of the cycle-by-cycle power limit function that is discussed in the Protection Features section.

7.4.2 Frequency Foldback Mode Control

Operation in FFM results in the application of constant volt-seconds to the flyback transformer during each switching cycle. During frequency foldback mode, as the load decreases, the MOSFET peak current is kept constant and the switching frequency is reduced (foldback) to reduce the output power. In this mode, the flyback converter will always operate in discontinuous conduction mode. When the FB voltage is between 1.4 V and
2.0 V, the voltage controlled oscillator restricts the operating frequency between 40 kHz and 130 kHz and the CS is clamped to 0.4 V, including the power limit offset. Valley detection is active during FFM.

7.4.3 Green-Mode Control

During green mode, the converter operates at a fixed switching frequency of 40 kHz and fixed peak current. The output power is adjusted by the converter ON/OFF durations, which is also known as burst mode. When the FB voltage is between 1.4 V and 0.5 V, the controller is commanding an excess of energy to be transferred to the load which in turn, drives the error higher and FB lower. When FB reaches 0.5 V, the OUT pulses are terminated and do not resume until FB reaches 0.7 V. In this mode, the converter operates in hysteretic control with the OUT pulse terminated at a fixed CS voltage level of 0.4 V. The power limit offset is turned OFF during Green mode and it returns to ON when FB is above 1.4 V. Green mode reduces the average switching frequency in order to minimize switching losses and increase the efficiency at light-load conditions.

7.4.4 Operating Mode Programming

Boundaries of the operating modes are programmed by the flyback transformer and the four components R_PL, R_CS, R_OVP1 and R_OVP2; shown in the Functional Block Diagram and Typical Application Diagram drawing.

The transformer characteristics that predominantly affect the modes are the magnetizing inductance of the primary and the magnitude of the output voltage, reflected to the primary. To a lesser degree (yet significant), the boundaries are affected by the MOSFET output capacitance and transformer leakage inductance. The design procedure here is to select a magnetizing inductance and a reflected output voltage that operates at the DCM/CCM boundary at maximum load and maximum line. The actual inductance should be noticeably smaller to account for the ring between the magnetizing inductance and the total stray capacitance measured at the drain of the power MOSFET. This programs the QR/DCM boundary of operation. All other mode boundaries are preset with the thresholds in the oscillator and green-mode blocks.

The four components R_PL, R_CS, R_OVP1 and R_OVP2 must be programmed as a set due to the interactions of the functions. The use of the UCC28600 design calculator, SLVC104, is highly recommended in order to achieve the desired results with a careful balance between the transformer parameters and the programming resistors.