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ZHCSE29A August 2015 – August 2015 UCC27714

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

D|14
- MPDS177H

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾ ⁽²⁾

Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to COM (unless otherwise noted), currents are positive into and negative out of the specified terminal. ⁽¹⁾

			MIN	MAX	UNIT
V_IN	Input voltage range	HI, LI, EN⁽³⁾ with respect to VSS	–5	20	V
		VDD supply voltage	–0.3	20	V
		HB	–0.3	640	V
		HB-HS	–0.3	20	V
V_OUT	Output voltage range, HO	DC	HS – 0.3	HB + 0.3	V
	Output voltage range, HO	Transient, less than 100 ns⁽⁴⁾	HS – 2	HB + 0.3	V
	Output voltage range, LO	DC	–0.3	VDD + 0.3	V
	Output voltage range, LO	Transient, less than 100 ns⁽⁴⁾	–2	VDD + 0.3	V
	Logic ground, With respect to COM		–7	6	V
	Logic ground, VDD-VSS		–0.3	20	V
I_OUT	Output current, HO, LO, IOUT_PULSED (100 ns)			±4	A
I_OUT	Output current, HO, LO, IOUT_DC			0.25	A
dV_HS/dt	Allowable offset supply voltage transient		–50	50	V/ns
	Lead temperature (soldering, 10 second)			300	°C
T_J	Junction temperature range		–40	150	°C
T_stg	Storage temperature range		-65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) See Packaging Section of the datasheet for thermal limitations and considerations of packages.

(3) The maximum voltage on the Input pins is not restricted by the voltage on the VDD pin.

(4) Values are verified by characterization on bench.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)^⁽¹⁾	Electrostatic discharge		Human body model, HBM	±1400	V
V_(ESD)^⁽¹⁾	Electrostatic discharge		Charge device model, CDM	±500	V

(1) These devices are sensitive to electrostatic discharge; follow proper device handing procedures

7.3 Recommended Operating Conditions

All voltages are with respect to COM, –40°C < T_J < 125°C, currents are positive into, negative out of the specified terminals

		MIN	MAX	UNIT
VDD	Supply voltage	10	18	V
HB-HS	Driver bootstrap voltage	10	18	V
HS	Source terminal voltage⁽¹⁾	–8	600	V
HB	Bootstrap pin voltage	HS + 10	HS + 18	V
HI, LI, EN	Input voltage with respect to VSS	–4	18	V
VSS	Logic ground	–6⁽²⁾	5⁽³⁾	V
T_J	Junction temperature	–40	125	°C

(1) Logic operational for HS of –8 V to 600 V at HB – HS = 12 V

(2) At VDD – COM = 10 V

(3) At VDD – COM = 15 V

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC27714	UNIT
		D (SOIC)
		PINS
R_θJA	Junction-to-ambient thermal resistance	72.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	31.8	°C/W
R_θJB	Junction-to-board thermal resistance	26.5	°C/W
ψ_JT	Junction-to-top characterization parameter	3.6	°C/W
ψ_JB	Junction-to-board characterization parameter	26.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

At VDD = VHB = 15 V, VSS = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < T_J < 125°C, current are positive into and negative out of the specified terminal, over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY BLOCK
V_VDD(on)	turn-on threshold voltage of VDD		8.4	9.1	9.8	V
V_VDD(off)	turn-off threshold voltage of VDD		7.9	8.6	9.3	V
V_VDD(hys)	Hysteresis of VDD		0.4	0.5	-	V
V_VHB(on)	turn-on threshold voltage of VHB-VHS		7.7	8.3	9.0	V
V_VHB(off)	turn-off threshold voltage of VHB-VHS		6.7	7.25	8.05	V
V_VHB(hys)	Hysteresis of VHB-VHS		0.5	1.0	-	V
I_QDD	Total quiescent VDD to VSS and COM supply current	HI = LI = 0 V or 5 V, DC on/off state		750	1050	µA
I_QCOM	Quiescent VDD-COM supply current	HI = LI = 0 V or 5 V, DC on/off state		175	350	µA
I_QVSS	Quiescent VDD-VSS supply current	HI = LI = 0 V or 5 V, DC on/off state		550	750	µA
I_QBS	Quiescent HB-HS supply current	HI = 0 V or 5 V, HO in DC on/off state		120	300	µA
I_BL	Bootstrap Supply Leakage Current	HB = HS = 600 V			20	µA
INPUT AND ENABLE BLOCK
V_INH, V_ENH	Input pin (HI or LI) and enable pin (EN) High threshold		1.7	2.3	2.7	V
V_INL, V_ENL	Input pin (HI or LI) and enable pin (EN) low threshold		1.2	1.6	2.1	V
V_INHYS, V_ENHYS	Input pin (HI or LI) and enable pin (EN) threshold hysteresis			0.7		V
I_INL	HI, LI input low bias current	HI, LI = 0 V	-5	0	5	µA
I_INH	HI, LI input high bias current	HI, LI = 5 V	3		65	µA
I_ENL	EN input low bias current	V_EN= 0 V	-90		-50	µA
I_ENH	EN input high bias current	V_EN = 5 V	-65		-25	µA
R_HI	Pull-down resistor on HI input pin			400		kΩ
R_LI	Pull-down resistor on LI input pin			400		kΩ
R_EN	Pull-up resistor on enable pin			200		kΩ
OUTPUT BLOCK
V_DD-V_LOH	LO output high voltage	LI = 5 V, I_LO = –20 mA		70	120	mV
V_HB-V_HOH	HO output high voltage	HI = 5 V, I_HO = –20 mA		70	120	mV
V_LOL	LO output low voltage	LI = 0 V, I_LO = 20 mA		15	35	mV
V_HOL	HO output low voltage	HI = 0 V, I_HO = 20 mA		20	40	mV
R_LOL, R_HOL ^⁽²⁾	LO, HO output pull down resistance	I_LO = 20 mA, I_HO= 20 mA			1.45	Ω
R_LOH, R_HOH	LO, HO output pull up resistance	I_LO = –20 mA, I_HO= –20 mA		3.75	5.8	Ω
I_GPK- ⁽¹⁾	HO. LO output low short circuit pulsed current	HI = L = 0 V, HO = LO = 15 V, PW < 10 µs		4		A
I_GPK+ ⁽¹⁾	HO. LO output high short circuit pulsed current	H I= LI = 5 V, HO = LO = 0 V, PW < 10 µs		4		A

(1) Ensured by Design, Not tested in production

(2) R_OH represents on-resistance of only the P-Channel MOSFET device in pull-up structure of UCC27714 output stage. Refer to Output Stage

7.6 Timing Requirements

		NOM	MAX	UNIT
DYNAMIC CHARACTERISTICS
t_PDLH	Turn-on propagation delay, LI to LO, HI to HO, HS = COM = 0 V or HS = 600 V	90	125	ns
t_PDHL	Turn-off propagation delay, LI to LO, HI to HO, HS = COM = 0 V or HS = 600 V	90	125	ns
t_PDRM	Low-to-high delay matching, HS = COM = 0 V		20	ns
t_PDFM	High-to-low delay matching, HS = COM = 0 V		20	ns
t_RISE	Turn-on rise time, 10% to 90%, HO/LO with 1000-pF load	15	30	ns
t_FALL	Turn-off fall time, 90% to 10%, HO/LO with 1000-pF load	15	30	ns
t_ON	Minimum HI/LI ON pulse that changes output state, 0-V to 5-V input signal on HI and LI pins		100	ns
t_OFF	Minimum HI/LI OFF pulse that changes output state, 5-V to 0-V input signal on HI and LI pins		100	ns

Figure 1. Typical Test Timing Diagram

7.7 Typical Characteristics

Figure 2. Low-Side, Turn-On Propagation Delay vs Temperature

Figure 4. High-Side, Turn-On Propagation Delay vs Temperature

Figure 6. Turn-On Delay Matching vs Temperature

Figure 8. High-Side, Turn-On Propagation Delay vs HS

Figure 10. LO Rise Time with 1000-pF Load vs Temperature

Figure 12. HO Rise Time with 1000-pF Load vs Temperature

Figure 14. VDD UVLO On Threshold vs Temperature

Figure 16. VHB-VHS UVLO On Threshold vs Temperature

Figure 18. VDD UVLO Hysteresis vs Temperature

Figure 20. HI/LI/EN Pin High Threshold vs Temperature

Figure 22. HI/LI/EN Pin Hysteresis vs Temperature

Figure 24. LO Output High Voltage with 20-mA Load vs Temperature

Figure 26. HO Output High Voltage with 20-mA Load vs Temperature

Figure 28. HO Output Pull-Down Resistance vs Temperature

Figure 30. HO Output Pull-Up Resistance vs Temperature

Figure 32. EN OFF Response Time vs Temperature

Figure 34. Quiescent VDD to COM Supply Current vs Temperature

Figure 36. Bootstrap Supply Leakage Current vs Temperature

Figure 3. Low-Side, Turn-Off Propagation Delay vs Temperature

Figure 5. High-Side, Turn-Off Propagation Delay vs Temperature

Figure 7. Turn-Off Delay Matching vs Temperature

Figure 9. High-Side, Turn-Off Propagation Delay vs HS

Figure 11. LO Fall Time with 1000-pF Load vs Temperature

Figure 13. HO Fall Time with 1000-pF Load vs Temperature

Figure 15. VDD UVLO Off Threshold vs Temperature

Figure 17. VHB-VHS UVLO Off Threshold vs Temperature

Figure 19. VHB-VHS UVLO Hysteresis vs Temperature

Figure 21. HI/LI/EN Pin Low Threshold vs Temperature

Figure 23. LO Output Low Voltage with 20-mA Load vs Temperature

Figure 25. HO Output Low Voltage with 20-mA Load vs Temperature

Figure 27. LO Output Pull-Down Resistance vs Temperature

Figure 29. LO Output Pull-Up Resistance vs Temperature

Figure 31. EN ON Response Time vs Temperature

Figure 33. Total Quiescent VDD to VSS and COM Supply Current vs Temperature

Figure 35. Quiescent VDD to VSS Supply Current vs Temperature

Figure 37. Total Quiescent HB to HS Supply Current