Table 1. UCC27531-Q1 Features and Benefits

8.3.1 VDD UVLO

The UCC27531-Q1 device has internal under voltage lockout (UVLO) protection feature on the VDD pin supply circuit blocks. To ensure an acceptable power dissipation in the power switch, this UVLO prevents the operation of the gate driver at low supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than V_ON during power-up and when VDD voltage is less than V_OFF during power down), this circuit holds all outputs LOW, regardless of the status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also when there are droops or dips in the VDD bias voltage when the system commences switching and there is a sudden increase in I_DD. The capability to operate at voltage levels such as 10 V to 32 V provides flexibility to drive Si MOSFETs, IGBTs, and emerging SiC FETs.

Figure 22. Power Up

8.3.2 Input Stage

The input pins of UCC27531-Q1 device are based on a TTL and CMOS compatible input threshold logic that is independent of the VDD supply voltage. With typical high threshold = 2 V and typical low threshold = 1 V, the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic. Wider hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. This device also features tight control of the input pin threshold voltage levels which eases system design considerations and guarantees stable operation across temperature. The very low input capacitance , typically 20 pF, on these pins reduces loading and increases switching speed.

The device features an important safety function wherein, whenever the input pin is in a floating condition, the output is held in the low state. This is achieved using pullup or pulldown resistors on the input pins as shown in the block diagrams.

The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be exercised whenever the driver is used with slowly varying input signals, especially in situations where the device is located in a separate daughter board or PCB layout has long input connection traces:

• High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. Since the device features just one GND pin which may be referenced to the power ground, this may interfere with the differential voltage between Input pins and GND and trigger an unintended change of output state. Because of fast 17 ns propagation delay, this can ultimately result in high-frequency oscillations, which increases power dissipation and poses risk of damage
• 1-V Input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.

If limiting the rise or fall times to the power device to reduce EMI is necessary, then an external resistance is highly recommended between the output of the driver and the power device instead of adding delays on the input signal. This external resistor has the additional benefit of reducing part of the gate charge related power dissipation in the gate driver device package and transferring it into the external resistor itself.

Finally, because of the unique input structure that allows negative voltage capability on the Input and Enable pins, caution must be used in the following applications:

• Input or Enable pins are switching to amplitude > 15 V
• Input or Enable pins are switched at dV/dt > 2 V/ns

8.3.3 Enable Function

The Enable (EN) pin of the UCC27531-Q1 has an internal pullup resistor to an internal reference voltage so leaving Enable floating turns on the driver and allows it to send output signals properly. If desired, the Enable can also be driven by low-voltage logic to enable and disable the driver.

8.3.4 Output Stage

The output stage of the UCC27531-Q1 device is illustrated in Figure 23. The UCC27531-Q1 device features a unique architecture on the output stage which delivers the highest peak source current when it is most needed during the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when the output changes state from low to high, the gate driver device is able to deliver a brief boost in the peak sourcing current enabling fast turn on.

Figure 23. UCC27531-Q1 Gate Driver Output Stage

Split output depicted in Figure 23. For devices with single OUT pin, OUTH and OUTL are connected internally and then connected to OUT.

The R_OH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the on-resistance of the P-Channel device only, because the N-Channel device is turned-on only during output change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is represented by ROH parameter. The pulldown structure is composed of a N-Channel MOSFET only. The ROL parameter (see Electrical Characteristics), which is also a DC measurement, is representative of true impedance of the pulldown stage in the device. In UCC27531-Q1, the effective resistance of the hybrid pullup structure is approximately 3 x R_OL.

The UCC27531-Q1 is capable of delivering 2.5-A source, and up to 5-A sink at VDD = 18 V. Strong sink capability results in a very low pulldown impedance in the driver output stage which boosts immunity against the parasitic Miller turn-on (high slew rate dV/dt turn on) effect that is seen in both IGBT and FET power switches .

An example of a situation where Miller turn on is a concern is synchronous rectification (SR). In SR application, the dV/dt occurs on MOSFET drain when the MOSFET is already held in Off state by the gate driver. The current charging the C_GD Miller capacitance during this high dV/dt is shunted by the pulldown stage of the driver. If the pulldown impedance is not low enough then a voltage spike can result in the V_GS of the MOSFET, which can result in spurious turn on. This phenomenon is illustrated in Figure 24.

Figure 24. Low Pulldown Impedance in UCC27531-Q1
(Output Stage Mitigates Miller Turn-on Effect)

The driver output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low impedance to switching overshoots and undershoots. This means that in many cases, external Schottky diode clamps may be eliminated.

Table 2. UCC27531QDBVRQ1 Input/Output Logic Truth Table (For Single Output Driver)