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ZHCS777F February 2012 – November 2014 UCC27511 , UCC27512

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DBV|6
- MPDS026Q

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾⁽³⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltage range	VDD	–0.3	20	V
OUTH voltage, (UCC27511)		–0.3	VDD + 0.3
OUTL voltage, (UCC27511)	DC	–0.3	20
OUTL voltage, (UCC27511)	Repetitive pulse less than 200 ns⁽⁵⁾	–2	20
OUT voltage, (UCC27512)	DC	–0.3	VDD + 0.3
OUT voltage, (UCC27512)	Repetitive pulse less than 200 ns⁽⁵⁾	–2	VDD + 0.3
Output continuous current (OUTH source current and OUTL sink current)	I_{OUT_DC}(source)		0.3	A
	I_{OUT_DC} (sink)		0.6
Output pulsed current (0.5 µs) (OUTH source current and OUTL sink current)	I_{OUT_pulsed}(source)		4
	I_{OUT_pulsed}(sink)		8
IN+, IN–⁽⁴⁾		–0.3	20	V
Lead temperature	Soldering, 10 sec.		300	°C
Lead temperature	Reflow		260	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into and negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages.

(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.

(4) Maximum voltage on input pins is not restricted by the voltage on the VDD pin.

(5) Values are verified by characterization on bench.

8.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–4000	4000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–1000	1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	TYP	MAX	UNIT
Supply voltage range, VDD	4.5	12	18	V
Operating junction temperature range	–40		140	°C
Input voltage, IN+ and IN-	0		18	V

8.4 Thermal Information

THERMAL METRIC		UCC27511	UCC27512	UNIT
		DBV	WSON⁽¹⁾
		6 PINS	6 PINS
θ_JA	Junction-to-ambient thermal resistance⁽²⁾	217.8	85.6	°C/W
θ_JCtop	Junction-to-case (top) thermal resistance⁽³⁾	97.6	100.1
θ_JB	Junction-to-board thermal resistance⁽⁴⁾	72.2	58.6
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	8.6	7.5
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	71.6	58.7
θ_JCbot	Junction-to-case (bottom) thermal resistance⁽⁷⁾	n/a	23.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

NOTE

Under identical power dissipation conditions, the DRS package will allow to maintain a lower die temperature than the DBV. θ_JA metric should be used for comparison of power dissipation capability between different packages (Refer to the Power Dissipation Section).

8.5 Electrical Characteristics

V_DD = 12 V, T_A = T_J = –40°C to 140°C, 1-µF capacitor from V_DD to GND. Currents are positive into, negative out of the specified terminal.

PARAMETER		TEST CONDITION		MIN	TYP	MAX	UNIT
BIAS CURRENTS
I_DD(off)	Startup current	VDD = 3.4 V	IN+ = VDD, IN– = GND	40	100	160	µA
			IN+ = IN– = GND or IN+ = IN– = VDD	25	75	145
			IN+ = GND, IN– = VDD	20	60	115
UNDERVOLTAGE LOCKOUT (UVLO)
V_ON	Supply start threshold	T_A = 25°C		3.91	4.20	4.5	V
V_ON	Supply start threshold	T_A = –40°C to 140°C		3.70	4.20	4.65
V_OFF	Minimum operating voltage after supply start			3.45	3.9	4.35
V_{DD_H}	Supply voltage hysteresis			0.2	0.3	0.5
INPUTS (IN+, IN-)
V_{IN_H}	Input signal high threshold	Output high for IN+ pin, Output low for IN– pin			2.2	2.4	V
V_{IN_L}	Input signal low threshold	Output low for IN+ pin, Output high for IN– pin		1.0	1.2
V_{IN_HYS}	Input signal hysteresis				1.0
SOURCE/SINK CURRENT
I_SRC/SNK	Source/sink peak current⁽¹⁾	C_LOAD = 0.22 µF, F_SW = 1 kHz			-4/+8		A
OUTPUTS (OUTH, OUTL, OUT)
V_DD-V_OH	High output voltage	VDD = 12 V I_OUTH = -10 mA			50	90	mV
V_DD-V_OH	High output voltage	VDD = 4.5 V I_OUTH = -10 mA			60	130
V_OL	Low output voltage	VDD = 12 I_OUTL = 10 mA			5	6.5
V_OL	Low output voltage	VDD = 4.5 V I_OUTL = 10 mA			5.5	10
R_OH	Output pull-up resistance⁽³⁾	VDD = 12 V I_OUTH = -10 mA			5.0	7.5	Ω
R_OH	Output pull-up resistance⁽³⁾	VDD = 4.5 V I_OUTH = -10 mA			5.0	11.0
R_OL	Output pull-down resistance	VDD = 12 V I_OUTL = 10 mA			0.375	0.650
R_OL	Output pull-down resistance	VDD = 4.5 V I_OUTL = 10 mA			0.45	0.750

(1) Ensured by Design.

(2) See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4.

(3) R_OH represents on-resistance of P-Channel MOSFET in pullup structure of the output stage of the UCC27511 and UCC27512.

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_R	Rise time⁽²⁾	VDD = 12 V C_LOAD = 1.8 nF, connected to OUTH and OUTL pins tied together		8	12	ns
t_R	Rise time⁽²⁾	VDD = 4.5 V C_LOAD = 1.8 nF		16	22
t_F	Fall time⁽²⁾	VDD = 12 V C_LOAD = 1.8 nF, connected to OUTH and OUTL pins tied together		7	11
t_F	Fall time⁽²⁾	VDD=4.5V C_LOAD = 1.8 nF		7	11
t_D1	IN+ to output propagation delay⁽²⁾	VDD = 12 V 5-V input pulse C_LOAD = 1.8 nF, connected to OUTH and OUTL pins tied together	4	13	23
t_D1	IN+ to output propagation delay⁽²⁾	VDD = 4.5 V 5-V input pulse C_LOAD = 1.8 nF, connected to OUTH and OUTL pins tied together	4	15	26
t_D2	IN- to output propagation delay⁽²⁾	VDD = 12 V C_LOAD = 1.8 nF, connected to OUTH and OUTL pins tied together	4	13	23
t_D2	IN- to output propagation delay⁽²⁾	VDD = 4.5 V C_LOAD = 1.8 nF, connected to OUTH and OUTL pins tied together	4	19	30