ZHCSTB0E February 2010 – November 2023 UCC27321-Q1 , UCC27322-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 說明（續）
- 5 Related Products
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Revision History
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- DGN|8
訂購信息
6 Pin Configuration and Functions
Figure 6-1 D
Package8-Pin SOICTop View
Figure 6-2 DGN Package8-Pin MSOP with
PowerPADTop ViewTable 6-1 Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AGND | 4 | GND | The AGND and the PGND must be connected by a single thick trace directly under the device. There must be a low ESR, low ESL capacitor of 0.1 μF between VDD (pin 1) and AGND. The power MOSFETs must be placed on the PGND side of the device while the control circuit must be on the AGND side of the device. The control circuit ground must be common with the AGND while the PGND must be common with the source of the power FETs. |
| ENBL | 3 | I | Enable input for the driver with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with a pullup resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state. |
| IN | 2 | I | Input signal of the driver, which has logic-compatible threshold and hysteresis. For UCC27321-Q1, IN is inverting, and for UCC37322-Q1, IN is noninverting. |
| OUT | 6, 7 | O | Driver outputs that must be connected together externally. The output stage is capable of providing 9-A peak drive current to the gate of a power MOSFET. |
| PGND | 5 | GND | Common ground for output stage. This ground must be connected very close to the source of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing effects due to output switching di/dt, which can affect the input threshold. There must be a low ESR, low ESL capacitor of 0.1 μF between VDD (pin 8) and PGND. |
| VDD | 1, 8 | PWR | Supply voltage and the power input connections for this device. These pins must be connected together externally. |
| PowerPAD | Pad | GND | PowerPAD on DGN package only. The PowerPAD thermal pad is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of the device. |