ZHCSDP7C May 2015 – July 2024 UCC27201A-Q1
PRODUCTION DATA
The input stages provide the interface to the PWM output signals. The input stages of the UCC27201A-Q1 incorporate an open drain configuration to provide the lower input thresholds. The input impedance is 68k? nominal and input capacitance is approximately 4pF. The 68k? is a pull-down resistance to VSS (ground). The logic level compatible input provides a rising threshold of 2.3V typical and a falling threshold of 1.6V typical.